MEMORY SYSTEM AND CONTROL METHOD FOR THE SAME

• US 20110083060A1
• Filed: 06/08/2010
• Published: 04/07/2011
• Est. Priority Date: 10/05/2009
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Uchikawa, Hironori, Sakurada, Kenji
• Granted Patent: US 8,250,437 B2
• Time in Patent Office: Days
• US Class Current: 714/763
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 29/00 Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation

Abstract

A memory system in an embodiment having a host and a memory card, including: a plurality of semiconductor memory cells, each cell being configured to store N-bit coded data based on threshold voltage distributions; an LLR table storage section configured to store a first LLR table that consists of normal LLR data corresponding to predetermined threshold voltages and a second LLR table that consists of LLR data such that two LLRs at each location corresponding to each location in the first LLR table at which a sign is inverted between two adjacent LLRs are “0”; and a decoder configured to perform decoding processing through probability-based repeated calculations using an LLR.

Claims

1. A memory system comprising:

a storage apparatus including a plurality of semiconductor memory cells, each cell being configured to store N-bit coded data based on 2^N (N is a natural number not smaller than

     2) threshold voltage distributions;

a storage section configured to store a first LLR table that consists of normal LLR data corresponding to predetermined threshold voltages and a second LLR table that consists of LLR data such that absolute values of two LLRs at each location corresponding to each location in the first LLR table at which a sign is inverted between two adjacent LLRs are different from absolute values of the respective LLRs in the first LLR table; and

a decoder configured to, when performing decoding processing through probability-based repeated calculations using an LLR calculated from the first or second LLR table and the threshold voltage,

perform the decoding processing using the LLR calculated from the second LLR table and the threshold voltage if the decoding processing using the LLR calculated from the first LLR table and the threshold voltage results in an error.

2. The memory system according to claim 1, wherein

N is not greater than 7.

3. The memory system according to claim 2, wherein

the absolute values of the two LLRs at the corresponding location in the second LLR table are smaller than the absolute values of the respective LLRs in the first LLR table.

4. The memory system according to claim 3, wherein

values of the two LLRs at the corresponding location in the second LLR table are both “

0.”

5. The memory system according to claim 2, wherein

a difference between the absolute values of the two LLRs at the corresponding location in the second LLR table is greater than a difference between the absolute values of the two LLRs at the location in the first LLR table at which the sign is inverted between the LLRs, and the absolute value of every LLR for threshold voltages on a high-voltage side in the two LLRs at the corresponding location is greater than the absolute value of the LLR on the other side, so that a case where the threshold voltage distributions are shifted to a low-voltage side is assumed.

6. The memory system according to claim 2, wherein

a difference between the absolute values of the two LLRs at the corresponding location in the second LLR table is greater than a difference between the absolute values of the two LLRs at the location in the first LLR table at which the sign is inverted between the LLRs, and the absolute value of every LLR for threshold voltages on a high-voltage side in the two LLRs at the corresponding location is smaller than the absolute value of the LLR on the other side, so that a case where the threshold voltage distributions are shifted to the high-voltage side is assumed.

7. The memory system according to claim 2, wherein

the second LLR table comprises:

a third LLR table in which a difference between the absolute values of the two LLRs at the corresponding location in the second LLR table is greater than a difference between the absolute values of the two LLRs at the location in the first LLR table at which the sign is inverted between the LLRs, and the absolute value of every LLR for threshold voltages on a high-voltage side in the two LLRs at the corresponding location is greater than the absolute value of the LLR on the other side, so that a case where the threshold voltage distributions are shifted to a low-voltage side is assumed; and

a fourth LLR table in which a difference between the absolute values of the two LLRs at the corresponding location in the second LLR table is greater than a difference between the absolute values of the two LLRs at the location in the first LLR table at which the sign is inverted between the LLRs, and the absolute value of every LLR for threshold voltages on the high-voltage side in the two LLRs at the corresponding location is smaller than the absolute value of the LLR on the other side, so that a case where the threshold voltage distributions are shifted to the high-voltage side is assumed, and wherein

the decoder performs the decoding processing using at least either one of the third LLR table and the fourth LLR table as the second LLR table.

8. The memory system according to claim 7, wherein

if the decoding processing using an LLR calculated from the third or fourth LLR table and the threshold voltage results in an error, the decoder performs the decoding processing using an LLR calculated from the other LLR table and the threshold voltage.

9. A control method for a memory system, comprising:

detecting threshold voltages of semiconductor memory cells, each cell storing N-bit coded data based on 2^N (N is a natural number not smaller than

     2) threshold voltage distributions;

calculating a first LLR from a first LLR table that consists of normal LLR data corresponding to predetermined threshold voltages and from the detected threshold voltages;

performing first LDPC decoding in which decoding processing is performed based on the first LLR;

calculating, if the first LDPC decoding fails, a second LLR from a second LLR table that consists of LLR data such that absolute values of two LLRs at each location corresponding to each location in the first LLR table at which a sign is inverted between two adjacent LLRs are smaller than absolute values of the respective LLRs in the first LLR table and from the detected threshold voltage; and

performing second LDPC decoding in which decoding processing is performed based on the second LLR.

10. The control method for a memory system according to claim 9, wherein

N is not greater than 7.

11. The control method for a memory system according to claim 10, wherein

the absolute values of the two LLRs at the corresponding location in the second LLR table are smaller than the absolute values of the respective LLRs in the first LLR table.

12. The control method for a memory system according to claim 11, wherein

values of the two LLRs at the corresponding location in the second LLR table are both “

0.”

13. The control method for a memory system according to claim 10, wherein

a difference between the absolute values of the two LLRs at the corresponding location in the second LLR table is greater than a difference between the absolute values of the two LLRs at the location in the first LLR table at which the sign is inverted between the LLRs, and the absolute value of every LLR for threshold voltages on a high-voltage side in the two LLRs at the corresponding location is greater than the absolute value of the LLR on the other side, so that a case where the threshold voltage distributions are shifted to a low-voltage side is assumed.

14. The control method for a memory system according to claim 10, wherein

a difference between the absolute values of the two LLRs at the corresponding location in the second LLR table is greater than a difference between the absolute values of the two LLRs at the location in the first LLR table at which the sign is inverted between the LLRs, and the absolute value of every LLR for threshold voltages on a high-voltage side in the two LLRs at the corresponding location is smaller than the absolute value of the LLR on the other side, so that a case where the threshold voltage distributions are shifted to the high-voltage side is assumed.

15. The control method for a memory system according to claim 10, wherein

the second LLR table comprises:

a third LLR table in which a difference between the absolute values of the two LLRs at the corresponding location in the second LLR table is greater than a difference between the absolute values of the two LLRs at the location in the first LLR table at which the sign is inverted between the LLRs, and the absolute value of every LLR for threshold voltages on a high-voltage side in the two LLRs at the corresponding location is greater than the absolute value of the LLR on the other side, so that a case where the threshold voltage distributions are shifted to a low-voltage side is assumed; and

a fourth LLR table in which a difference between the absolute values of the two LLRs at the corresponding location in the second LLR table is greater than a difference between the absolute values of the two LLRs at the location in the first LLR table at which the sign is inverted between the LLRs, and the absolute value of every LLR for threshold voltages on the high-voltage side in the two LLRs at the corresponding location is smaller than the absolute value of the LLR on the other side, so that a case where the threshold voltage distributions are shifted to the high-voltage side is assumed, and wherein

the decoding processing is performed using at least either one of the third LLR table and the fourth LLR table as the second LLR table.

16. The control method for a memory system according to claim 15, wherein

if the decoding processing using an LLR calculated from the third or fourth LLR table and the threshold voltage results in an error, the decoding processing is performed using an LLR calculated from the other LLR table and the threshold voltage.

17. The control method for a memory system according to claim 10, wherein

the second LDPC decoding is preferentially used over the first LDPC decoding if the number of times of reading reaches a predetermined number or more.

18. The control method for a memory system according to claim 10, wherein

an upper limit value of the number of iterations of the first LDPC decoding is smaller than an upper limit value of the number of iterations of the second LDPC decoding.

19. A memory system comprising:

a storage apparatus including a plurality of NAND-type semiconductor memory cells, each cell being configured to store N-bit coded data based on 2^N (N is a natural number not smaller than 2 but not greater than

     7) threshold voltage distributions;

an LLR table storage section configured to store a first LLR table that consists of normal LLR data corresponding to average threshold voltage distributions for many semiconductor memory cells and a second LLR table in which values of two LLRs at each location corresponding to each location in the first LLR table at which a sign is inverted between two adjacent LLRs are both “

0”

; and

a decoder configured to, when performing LDPC decoding processing through probability-based repeated calculations using an LLR calculated from the first or second LLR table and the threshold voltage, perform the decoding processing using the LLR calculated from the second LLR table adapted for a shift of the threshold voltage distributions and from the threshold voltage if the decoding processing using the LLR calculated from the first LLR table and the threshold voltage results in an error.