HIGH VOLTAGE WIRE BOND FREE LEDS

• US 20110084294A1
• Filed: 10/15/2010
• Published: 04/14/2011
• Est. Priority Date: 11/14/2007
• Status: Active Grant

• Current Assignee: Creeled Incorporated
• Original Assignee: CREE Incorporated (Wolfspeed, Inc.)
• Inventors: Yao, Zhimin Jamie
• Granted Patent: US 8,536,584 B2
• Time in Patent Office: Days
• US Class Current: 257/93
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/32257 the layer connector connecting to a bonding area disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 27/153 in a repetitive configuration, e.g. LED bars
• CPC Class Codes: H01L 27/156 two-dimensional arrays
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01087 Francium [Fr]
• CPC Class Codes: H01L 33/20 with a particular shape, e.g. curved or truncated substrate
• CPC Class Codes: H01L 33/22 Roughened surfaces, e.g. at the interface between epitaxial layers
• CPC Class Codes: H01L 33/38 with a particular shape
• CPC Class Codes: H01L 33/405 Reflective materials
• CPC Class Codes: H01L 33/62 Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Abstract

An LED chip and method of fabricating the same is disclosed that comprises a plurality of sub-LEDs, said sub-LEDs interconnected such that the voltage necessary to drive said sub-LEDs is dependent on the number of said interconnected sub-LEDs and the junction voltage of said sub-LEDs. Each of said interconnected sub-LEDs comprising an n-type semiconductor layer, a p-type semiconductor layer, and an active or quantum well region interposed between the n-type and p-type layers. The monolithic LED chip further comprising a p-electrode having a lead that is accessible from a point on a surface opposite of a primary emission surface of the monolithic LED chip, the p-electrode electrically connected to the p-type layer, and an n-electrode having a lead that is accessible from a point on the surface opposite of the primary emission surface, the n-electrode electrically connected to the n-type layer. These sub-LEDs interconnected by at least a metallization layer on the n-type and p-type layers, which is insulated so that it does not short the sub-LEDs. Further, the LED chip is capable of being electrically coupled for operation without wire bonds.

Claims

1. A monolithic LED chip, comprising:

a plurality of sub-LEDs, said sub-LEDs interconnected without wire bonds such that the voltage necessary to drive said sub-LEDs is dependent on the number of said interconnected sub-LEDs and the junction voltage of said sub-LEDs; and

wherein said monolithic LED chip is capable of being electrically coupled for operation without wire bonds.

2. The monolithic LED chip of claim 1, wherein each of said sub-LEDs comprises a plurality of semiconductor layers and an active region interposed between said plurality of semiconductor layers.

3. The monolithic LED chip of claim 2 further wherein said plurality of semiconductor layers comprises at least an n-type semiconductor layer and a p-type semiconductor layer.

4. The monolithic LED chip of claim 2 further comprising a p-electrode accessible from a point on a surface opposite of a primary emission surface of said monolithic LED chip and an n-electrode having a lead that is accessible from a point on said surface opposite of said primary emission surface.

5. The monolithic LED chip of claim 4, wherein said p-electrode and said n-electrode are electrically coupled to said semiconductor layers such that a single applied to said p- and n-electrodes causes said sub-LEDs to emit light.

6. The monolithic LED chip of claim 3, further comprising electrically conductive and electrically insulating features to interconnect said sub-LEDs.

7. The monolithic LED chip of claim 6, wherein said electrically conductive features further comprise at least one metallization layer on at least a portion of said plurality of semiconductor layers to interconnected sub-LEDs and said electrically insulating features further comprise at least one insulator layer between at least a portion of said metallization layer and say n-type and p-type semiconductor layers.

8. The monolithic LED chip of claim 7, further comprising vias provided through at least a portion of said at least one insulator layer electrically connecting said p-electrode and said n-electrode to said metallization layer.

9. The monolithic LED chip of claim 6, wherein said electrically conductive features are internal to said LED chip.

10. The monolithic LED chip of claim 6, wherein said electrically insulating features insulate said electrically conductive features from other portions of said LED chip to prevent shorting of said electrically conductive features.

11. The monolithic LED chip of claim 3, further comprising an n-contact pad contacting said n-type semiconductor layer and providing an electrical connection between said n-type semiconductor layer and said n-electrode.

12. The monolithic LED chip of claim 3, further comprising a p-contact pad contacting said p-type semiconductor layer and providing an electrical connection between said p-type semiconductor layer and said p-electrode.

13. The monolithic LED chip of claim 12, wherein said p-contact pad functions as a current spreading layer.

14. The monolithic LED chip of claim 12, wherein said p-contact pad comprises a reflective material.

15. The monolithic LED chip of claim 12, further comprising a reflective material on the side of said p-contact pad facing the primary emission surface.

16. The monolithic LED chip of claim 15, further comprising a barrier material surrounding the reflective material on all sides except the side facing said primary emission surface.

17. The monolithic LED chip of claim 15 wherein said reflective material is electrically conductive.

18. The monolithic LED chip of claim 16, wherein the reflective material and barrier material are electrically conductive.

19. The monolithic LED chip of claim 1, wherein each of said sub-LEDs are formed from a single junction LED.

20. The monolithic LED chip of claim 19, wherein each of said sub-LEDs are formed from a single junction LED by removing portions of said single junction LED.

21. The monolithic LED chip of claim 19, wherein the active area utilization ratio is greater than 50%.

22. The monolithic LED chip of claim 19, wherein the active area utilization ratio is greater than 75%.

23. The monolithic LED chip of claim 3, further comprising a phosphor layer disposed opposite said leads of said n- and p-electrodes such that said phosphor layer comprises said primary emitting surface.

24. The monolithic LED chip of claim 3, wherein the primary emission surface is a substrate.

25. The monolithic LED chip of claim 24, wherein said substrate is comprised of an insulating material.

26. The monolithic LED chip of claim 3, wherein the primary emission surface is said n-type layer.

27. The monolithic LED chip of claim 3, wherein the primary emission surface is said p-type layer.

28. The monolithic LED chip of claim 1, emitting a white light from said sub-LEDs.

29. The monolithic LED chip of claim 1, emitting down converted light from said sub-LEDs.

30. The monolithic LED chip of claim 1, wherein the remaining ones of said serially connected sub-LEDs are capable of emitting light in response to said drive voltage when one of said sub-LEDs fails.

31. The monolithic LED chip of claim 7, wherein said insulator layers comprise dielectric materials.

32. The monolithic LED chip of claim 7, wherein said insulator layers comprise a polymer.

33. The monolithic LED chip of claim 7, wherein said insulator layers comprise an inorganic material.

34. The monolithic LED chip of claim 33, wherein said inorganic material comprises silicon nitride or silicon oxide.

35. The monolithic LED chip of claim 2, wherein said plurality of semiconductor layers and said active region comprise materials from the Group-III Nitrides.

36. A method for fabricating a monolithic LED chip, comprising:

providing a single junction LED on a submount, said single junction LED including first and second semiconductor layers;

separating said single junction LED into a plurality of sub-LEDs; and

serially interconnecting said sub-LEDs without wire bonds such that the voltage necessary to drive said sub-LEDs is dependent on the number of said serially interconnected sub-LEDs and the junction voltage of said sub-LEDs.

37. The method of claim 36, further comprising:

exposing a portion of the surface of said first semiconductor layer opposite said growth substrate;

forming a insulating layer on said second semiconductor layer and said exposed portion of said first semiconductor layer;

removing a portion of said insulating layer such that a portion of said first and second semiconductor layers is exposed;

forming an electrode layer on the remaining portions of said insulating layer and the exposed portions of said first and second semiconductor layers; and

removing a portion of said electrode layer to form first and second electrodes such that said first electrode is electrically contacting said first semiconductor layer and said second electrode is electrically contacting said second semiconductor layer, said first and second electrodes disposed to be electrically isolated from one another and from said active region.

38. The method of claim 36, further comprising forming a reflective layer on a surface of said second semiconductor layer opposite said active region.

39. The method of claim 36, further comprising forming a phosphor layer on said submount.

40. The method of claim 36, wherein said single junction LED is separated into sub-LEDs by removing portions of said single junction LED.

41. The method of claim 36, wherein portions of said single junction LED are removed by photolithography and etching.

42. The method of claim 36, further comprising forming electrically conductive and electrically insulating features to serially interconnect said sub-LEDs.

43. The method of claim 42, wherein said conductive features comprise connector traces.

44. The method of claim 36, further comprising forming bottom contacts between said sub-LEDs and said submount.

45. The method of claim 38, wherein the active area utilization ratio is greater than 50%.

46. The method of claim 38, wherein the active area utilization ratio is greater than 75%.

47. The method of claim 36, where said sub-LEDs are flip-chip mounted on said submount.

48. A LED chip, comprising:

a plurality of sub-LEDs on a submount, wherein said sub-LEDs are formed from a single junction LED;

electrically conductive and electrically insulating features interconnecting said sub-LEDs such that an electrical current applied to said sub-LEDs spreads to all said sub-LEDs, wherein said LED chip is capable of being electrically coupled for operation without wire bonds.

49. The LED chip of claim 48, wherein the voltage necessary to drive said sub-LEDs is dependent on the number of said interconnected sub-LEDs and the junction voltage of said sub-LEDs.

50. The LED chip of claim 48, wherein said sub-LEDs are formed from a single junction LED by removing portions of said single junction LED.

51. The LED chip of claim 50, wherein the active area utilization ratio is greater than 50%.

52. The LED chip of claim 50, wherein the active area utilization ratio of said single junction LED active region is greater than 75%.

53. The LED chip of claim 48, wherein said electrically conductive features are comprised of at least one metallization layer placed on at least a portion of a light emission area of said sub-LED'"'"'s, opposite a primary light emission surface, said at least one metallization layer insulated such that it does not short circuit said sub-LEDs.

54. The LED chip of claim 48, wherein said sub-LEDs are flip-chip mounted on said submount.

55. A LED chip, comprising:

a plurality of sub-LEDs on a submount;

a plurality of bottom contacts, each of which is located on a surface opposite of a primary light emission surface of said sub-LEDs;

metallization layers placed on at least a portion of a light emission area of said sub-LEDs, opposite said primary light emission surface, interconnecting said sub-LEDs; and

insulating features to insulate portions of said sub-LEDs from said metallization layers.

56. The LED chip of claim 55, wherein said the drive voltage is dependent on the number of said interconnected sub-LEDs and the junction voltage of said sub-LEDs.

57. The LED chip of claim 55, wherein said primary light emission surface comprises a modified surface to increase light extraction from said LED chip.

58. The LED chip of claim 57, wherein said modified surface has been textured.

59. The LED chip of claim 55, further comprising conductive implants for making electrical connection to said sub-LEDs.

60. The LED chip of claim 55, further comprising a phosphor layer disposed over at least a portion of said primary light emission surface, said phosphor layer constituting at least a portion of said top surface of said LED chip and said sub-LEDs.

61. The LED chip of claim 60, wherein said sub-LEDs further comprise sidewalls;

said phosphor layer further disposed over at least a portion of said sidewalls; and

said phosphor layer further constituting at least a portion of said sidewalls of said LED chip and said sub-LEDS.