TRENCH TERMINATION STRUCTURE

• US 20110084332A1
• Filed: 10/08/2009
• Published: 04/14/2011
• Est. Priority Date: 10/08/2009
• Status: Abandoned Application

• Current Assignee: Vishay General Semiconductor LLC (Vishay Intertechnology Incorporated)
• Original Assignee: Vishay General Semiconductor LLC (Vishay Intertechnology Incorporated)
• Inventors: Kao, Lung-Ching
• Application Number:
  US12/575,517
• Publication Number:
  US 20110084332A1
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 29/0661 specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/66143 Schottky diodes
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/8725 of the trench MOS barrier type [TMBS]

Abstract

A trench MOS device includes a base semiconductor substrate, an epitaxial layer grown on the base semiconductor substrate, a first trench in the epitaxial layer, and a stepped trench comprising a second trench and a third trench in the epitaxial layer. There is a mesa between the first trench and the stepped trench. There is a spacer on a the sidewall of the second trench, wherein the third trench having a depth below the spacer. There is a dielectric layer extending along sidewalls and bottom walls of the second trench and the third trench. There is also a metal layer extending over the first trench, over a sidewall of the stepped trench and a portion of the bottom of the stepped trench.

Claims

1. A trench MOS device comprising:

a base semiconductor substrate;

an epitaxial layer grown on the base semiconductor substrate;

a first trench in the epitaxial layer;

a stepped trench comprising a second trench and a third trench in the epitaxial layer;

a mesa between the first trench and the stepped trench;

a spacer on a the sidewall of the second trench, wherein the third trench having a depth below the spacer;

a dielectric layer extending along sidewalls and bottom walls of the second trench and the third trench; and

a metal layer extending over the first trench, over a sidewall of the stepped trench and a portion of the bottom of the stepped trench.

2. The trench MOS device of claim 1 wherein the third trench extends downward about 2 micrometers below the second trench.

3. The trench MOS device of claim 2 wherein the base semiconductor subtrate is an N+ type base substrate.

4. The trench MOS device of claim 3 wherein the epitaxial layer is an N type epitaxial layer.

5. A trench MOS device and termination structure comprising:

an N+ type base substrate layer;

an N type epitaxial layer;

a first trench in the epitaxial layer wherein the interior surfaces of the first trench being coated with an insulative layer and filled with a first conductive layer;

a stepped termination trench comprised of a second and third trench wherein the first step is partially filled with a spacer comprised of a first conductive material;

a dielectric layer covering at least a portion of the spacer, and the sidewalls and bottom surface of the third trench; and

a second conductive layer covering the filled first trenches, a portion of the spacer, and a portion of the dielectric layer.

6. The trench MOS device of claim 5 wherein the second trench extends downward to approximately a depth of the spacer and wherein the third trench extends downward substantially from the spacer to thereby reduce electric field beneath the spacer.

7. The trench MOS device of claim 5 wherein the third trench extends downward about 2 micrometers below the second trench.

8. The trench MOS device of claim 5 further comprising an anode layer covering at least a portion of the second conductive layer.

9. A method for manufacturing a trench MOS device comprising etching a third trench between spacers of a second trench, to form a stepped trench comprising the second trench and the third trench and to thereby provide a stepped trench MOS device.

10. A method of simultaneously fabricating trench MOS devices and termination structure comprising:

providing a semiconductor substrate having a first layer and a second layer wherein the second layer is formed epitaxially on the first layer, the first layer being high doped with a conductive impurity level and the second layer being doped to a lower conductive impurity level;

coating the second layer in a hard mask layer;

forming an oxide on the hard mask layer by chemical vapor deposition wherein the oxide is between 2,000 and 10,000 Å

;

etching a first trench and a second trench where the first trench is separated from the second trench by a mesa and wherein the second trench stretches from a boundary of an active region to an end of the semiconductor substrate;

removing the oxide;

growing a gate oxide layer with a thickness between 150 A and 3,000 A on the sidewalls and bottoms of the first trenches and the second trench through a high temperature oxidation process;

depositing a first conductive layer through CVD on the gate oxide which fills the first trench and the second trench to a level higher than the mesa;

anistrophically etching the portion of the first conductive layer above the mesa surface and from a center section of the second trench leaving spacers of the first conductive layer on a portion of the sidewalls and bottom of the second trench;

etching a third trench between the spacers of the second trench;

depositing a dielectric layer over a portion of a spacer and the sidewalls and bottom of the third trench;

depositing a second conductive layer through a sputtering process over at least a portion of the dielectric layer.