Apparatus and Method for Through Silicon via Impedance Matching

• US 20110084358A1
• Filed: 10/08/2009
• Published: 04/14/2011
• Est. Priority Date: 10/08/2009
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Yang, Jeong Hwan, Nowak, Matthew M., Kim, Jonghae
• Granted Patent: US 8,618,629 B2
• Time in Patent Office: Days
• US Class Current: 257/531
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06544 Design considerations for via connections, e.g. geometry or layout
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/645 Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

Methods and apparatuses for matching impedances in a flip-chip circuit assembly are presented. An apparatus for matching impedances in a flip-chip circuit assembly may include a first circuit associated with a first die and a through silicon via (TSV) coupling the first circuit to a second circuit. The apparatus may further include a first impedance matching inductor interposed between the TSV and the second circuit. A method for matching impedances in a flip-chip circuit assembly may include providing a die having a first circuit, and forming a TSV over the die. The method may further include providing a second circuit and forming a first impedance matching inductor interposed between the TSV and second circuit.

Claims

1. An apparatus for matching impedances in a flip-chip circuit assembly, comprising:

a first circuit associated with a first die;

a through silicon via (TSV) coupling the first circuit to a second circuit; and

a first impedance matching inductor interposed between the TSV and the second circuit.

2. The apparatus of claim 1, further comprising:

a second impedance matching inductor interposed between the through silicon via and the first circuit.

3. The apparatus of claim 2, wherein the second impedance matching inductor is formed in a metal layer in the first die.

4. The apparatus of claim 2, wherein the first and second impedance matching inductors are part of an RF impedance matching circuit compensating the parasitic capacitance of the TSV.

5. The apparatus of claim 1, wherein the first impedance matching inductor is formed in a Re-Distributed Layer (RDL).

6. The apparatus of claim 1, wherein the second circuit is associated with a second die.

7. The apparatus of claim 6, wherein the second die is placed on the first die in a three-dimensional flip chip configuration.

8. The apparatus of claim 1, wherein the first circuit and second circuit operate at RF frequencies.

9. The apparatus of claim 1, wherein the first die is fabricated using a Complimentary Metallic Oxide Semiconductor (CMOS) process.

10. The apparatus of claim 1 further including a device, selected from the group consisting of a set top box, music player, video player, entertainment unit, navigation device, communications device, personal digital assistant (PDA), fixed location data unit, and a computer, into which the apparatus is integrated.

11. A method for matching impedances in a flip-chip circuit assembly, comprising:

providing a die having a first circuit;

forming a through silicon via (TSV) over the die;

providing a second circuit; and

forming a first impedance matching inductor interposed between the TSV and second circuit.

12. The method of claim 11, further comprising:

determining whether to compensate the TSV using a second impedance matching inductor; and

forming the second impedance matching inductor in between the TSV and the first circuit.

13. The method of claim 12, further comprising:

forming the second impedance matching inductor in a metal layer associated with the die.

14. The method of claim 12, wherein the first and second impedance matching inductors are part of an RF impedance matching circuit compensating the parasitic capacitance of the TSV.

15. The method of claim 11, further comprising:

forming the first impedance matching inductor in a Re-Distributed Layer (RDL).

16. The method of claim 11, further comprising:

forming the first impedance matching inductor using a Complimentary Metallic Oxide Semiconductor (CMOS) process.

17. The method of claim 11, wherein the die is associated with a three-dimensional flip chip process.

18. The method of claim 11, wherein the first circuit and second circuit operate at RF frequencies.

19. The method of claim 11, wherein the die is fabricated using a Complimentary Metallic Oxide Semiconductor (CMOS) process.

20. A method for matching impedances in a flip-chip circuit assembly, comprising:

step for providing a die having a first circuit;

step for forming a through silicon via (TSV) over the die;

step for providing a second circuit; and

step for forming a first impedance matching inductor interposed between the TSV and second circuit.

21. The method of claim 20, further comprising:

step for determining whether to compensate the TSV using a second impedance matching inductor; and

step for forming the second impedance matching inductor in between the TSV and the first circuit.

22. The method of claim 20, further comprising:

step for forming the first impedance matching inductor in a Re-Distributed Layer (RDL).

23. The method of claim 20, further comprising:

step for forming the first impedance matching inductor using a Complimentary Metallic Oxide Semiconductor (CMOS) process.

24. An apparatus for matching impedances in a flip-chip circuit assembly, comprising:

a first circuit associated with a first die;

means for coupling the first circuit to a second circuit; and

a first means for impedance matching interposed between the coupling means and the second circuit.

25. The apparatus of claim 24, further comprising:

a second means for impedance matching interposed between the coupling means and the first circuit.

27. The apparatus of claim 25, wherein the second means for impedance matching is formed in a metal layer in the first die.

28. The apparatus of claim 25, wherein the first means and second means for impedance matching are part of a means for compensating the parasitic capacitance of the coupling means.

29. The apparatus of claim 24, wherein the first means for impedance matching is formed in a Re-Distributed Layer (RDL).

30. The apparatus of claim 24, wherein the second circuit is associated with a second die.

31. The apparatus of claim 24, wherein the first circuit and second circuit operate at RF frequencies.

32. The apparatus of claim 24, wherein the first die is fabricated using a Complimentary Metallic Oxide Semiconductor (CMOS) process.

33. The apparatus of claim 24, wherein the second die is placed on the first die in a three-dimensional flip chip configuration.

34. The apparatus of claim 24 further including a device, selected from the group consisting of a set top box, music player, video player, entertainment unit, navigation device, communications device, personal digital assistant (PDA), fixed location data unit, and a computer, into which the apparatus is integrated.