Through Silicon Via (TSV) Wire Bond Architecture

• US 20110084365A1
• Filed: 07/16/2010
• Published: 04/14/2011
• Est. Priority Date: 10/09/2009
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yeh, Wei-Chih, Law, Oscar M.K., Wu, Kuo H.
• Granted Patent: US 8,264,067 B2
• Time in Patent Office: Days
• US Class Current: 257/621
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/05556 in side view
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/17181 On opposite sides of the body
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/45147 Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/48599 Principal constituent of the connecting portion of the wire connector being Gold (Au)
• CPC Class Codes: H01L 2224/48699 Principal constituent of the connecting portion of the wire connector being Aluminium (Al)
• CPC Class Codes: H01L 2224/48799 Principal constituent of the connecting portion of the wire connector being Copper (Cu)
• CPC Class Codes: H01L 2224/73257 Bump and wire connectors
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/5286 : Arrangements of power or ground buses
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/00015 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed as prior art
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01077 : Iridium [Ir]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor

Abstract

A through silicon via architecture for integrated circuits is provided. The integrated circuit (IC) includes a substrate with a top surface and a bottom surface with circuitry formed on the top surface, a plurality of bonding pads formed along a periphery of the bottom surface, and a backside metal layer (BML) formed on the bottom surface and electrically coupled to a second subset of bonding pads in the plurality of bonding pads. A first subset of bonding pads in the plurality of bonding pads is electrically coupled to circuitry on the top surface with through silicon vias (TSV). The BML distributes electrical signals provided by the second subset of bonding pads.

Claims

1. An integrated circuit (IC) comprising:

a substrate with a top surface and a bottom surface, wherein circuitry is formed on the top surface;

a plurality of bonding pads formed along a periphery of the bottom surface, wherein a first subset of bonding pads in the plurality of bonding pads is electrically coupled to circuitry on the top surface with through silicon vias (TSV); and

a backside metal layer (BML) formed on the bottom surface and electrically coupled to a second subset of bonding pads in the plurality of bonding pads, the BML configured to distribute electrical signals provided by the second subset of bonding pads.

2. The IC of claim 1, wherein each TSV coupled to bonding pads in the first subset of bonding pads comprises:

a first conductive pad formed on the bottom surface;

a second conductive pad formed on the top surface; and

a conductive member electrically coupling the first conductive pad to the second conductive pad, the conductive member formed in a hole formed in the substrate.

3. The IC of claim 2, wherein the first conductive pad, the second conductive pad, and the conductive member are arranged in a linear fashion.

4. The IC of claim 1, wherein the bonding pads in the second subset of bonding pads are either coupled to electrical ground or a first voltage potential.

5. The IC of claim 4, wherein the BML comprises conductors arranged in a grid pattern.

6. The IC of claim 5, wherein conductors in the BML are connected to TSVs coupled to circuitry formed on the top surface to distribute electrical ground or the first voltage potential to circuitry formed on the top surface.

7. The IC of claim 6, wherein conductors in the BML are formed to a thickness that is at least two times greater than a thickness of conductors formed on the top layer.

8. The IC of claim 5, wherein the BML further comprises at least one bump pad coupled to a TSV, the bump pad to permit electrical coupling between the IC and an attached IC or an external substrate.

9. The IC of claim 1, wherein the BML is formed within a boundary created by the plurality of bonding pads.

10. An integrated circuit (IC) comprising:

a substrate with a top surface and a bottom surface, wherein circuitry is disposed on the top surface;

a first bonding pad disposed on the bottom surface, the first bonding pad electrically coupled to circuitry on the top surface with a through silicon via (TSV); and

a backside metal layer (BML) disposed on the bottom surface and electrically coupled to a second bonding pad disposed on the bottom surface, the BML configured to distribute a first signal provided by the second bonding pad.

11. The IC of claim 10, wherein the second bonding pad is electrically coupled to the BML through two TSVs.

12. The IC of claim 11, wherein a first TSV conveys the first signal on the second bonding pad to the top surface and a second TSV conveys the first signal to the BML.

13. The IC of claim 12, wherein the first TSV and the second TSV are electrically coupled by a conductor.

14. The IC of claim 10, wherein the BML is further configured to distribute a second signal provided by a third bonding pad.

15. The IC of claim 14, wherein the third bonding pad is directly coupled to the BML.

16. The IC of claim 10, further comprising a power ring disposed about a periphery of the substrate, the power ring to distribute power to circuitry formed on the top surface.

17. A three-dimensional stacked multi-chip module comprising:

a first integrated circuit (IC) comprising a first substrate with a first top surface and a first bottom surface, wherein circuitry is formed on the first top surface;

a second IC, the second IC comprising,

a second substrate with a second top surface and a second bottom surface, wherein circuitry is formed on the second top surface,

a first plurality of bonding pads formed along a periphery of the second bottom surface, wherein a first subset of bonding pads in the first plurality of bonding pads is electrically coupled to circuitry on the second top surface with through silicon vias (TSV), and

a backside metal layer (BML) formed on the second bottom surface and electrically coupled to a second subset of bonding pads in the plurality of bonding pads, the BML configured to distribute electrical signals provided by the second subset of bonding pads; and

wherein the first IC is attached to the second IC.

18. The three-dimensional stacked multi-chip module of claim 17, wherein the first top surface of the first IC is attached to the second bottom surface of the second IC.

19. The three-dimensional stacked multi-chip module of claim 17, wherein bond wires are used to electrically couple each of the bonding pads in the plurality of bonding pads to external signals.

20. The three-dimensional stacked multi-chip module of claim 17, wherein the first IC further comprises:

a second plurality of bonding pads formed along a periphery of the first bottom surface, wherein a third subset of bonding pads in the second plurality of bonding pads are electrically coupled to circuitry on the first top surface with TSVs; and

a backside metal layer (BML) formed on the first bottom surface and electrically coupled to a fourth subset of bonding pads in the plurality of bonding pads, the BML configured to distribute electrical signals provided by the fourth subset of bonding pads.

21. The three-dimensional stacked multi-chip module of claim 20, wherein bond wires are used to electrically couple each of the bonding pads in the second plurality of bonding pads with external signals.