PACKAGE CARRIER, SEMICONDUCTOR PACKAGE, AND PROCESS FOR FABRICATING SAME

• US 20110084372A1
• Filed: 10/14/2010
• Published: 04/14/2011
• Est. Priority Date: 10/14/2009
• Status: Abandoned Application

• Current Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Original Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Inventors: HUANG, SHIH-FU, SU, YUAN-CHANG, CHEN, CHIA-CHENG
• Application Number:
  US12/904,876
• Publication Number:
  US 20110084372A1
• Time in Patent Office: Days
• US Class Current: 257/676
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/68345 used as a support during the manufacture of self supporting substrates
• CPC Class Codes: H01L 2221/68359 used as a support during manufacture of interconnect decals or build up layers
• CPC Class Codes: H01L 2224/27013 for holding or confining the layer connector, e.g. solder flow barrier
• CPC Class Codes: H01L 2224/32188 the layer connector connecting to a bonding area protruding from the surface of the item
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48106 the connector being orthogonal to a side surface of the semiconductor or solid-state body, e.g. parallel layout
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48228 the bond pad being disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/484 Connecting portions
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/92247 the second connecting process involving a wire connector
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/85 : using a wire connector wire bonding in general B23K20/004
• CPC Class Codes: H01L 24/92 : Specific sequence of method steps
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/06 : Polymers polymers per se C08; polymer adhesives C09J
• CPC Class Codes: H01L 2924/0665 : Epoxy resin
• CPC Class Codes: H01L 2924/07025 : Polyimide
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation

Abstract

A package carrier includes: (1) a dielectric layer; (2) a first electrically conductive pattern, embedded in the dielectric layer and disposed adjacent to a first surface of the dielectric layer, and including a plurality of first pads; (3) a plurality of first electrically conductive posts, extending through the dielectric layer, wherein each of the first electrically conductive posts includes a first electrically conductive post segment connected to at least one of the first pads and a second electrically conductive post segment connected to the first electrically conductive post segment, and a lateral extent of the first electrically conductive post segment is different from a lateral extent of the second electrically conductive post segment; and (4) a second electrically conductive pattern, disposed adjacent to a second surface of the dielectric layer, and including a plurality of second pads connected to respective ones of the second electrically conductive post segments.

Claims

1. A package carrier, comprising:

a dielectric layer having a plurality of openings;

a first conductive pattern, disposed adjacent to a first surface of the dielectric layer, the first conductive pattern including a plurality of first pads; and

a plurality of conductive vias disposed in respective ones of the openings, wherein each conductive via includes a first via segment, connected to at least one of the first pads, and a second via segment, connected to the first via segment, such that a lateral extent of the first via segment is different from a lateral extent of the second via segment.

2. The package carrier as claimed in claim 1, wherein the first conductive pattern is embedded in the dielectric layer.

3. The package carrier as claimed in claim 1, wherein the lateral extent of the first via segment is greater than the lateral extent of the second via segment.

4. The package carrier as claimed in claim 1, wherein the conductive vias provide a locking mechanism with respect to the dielectric layer.

5. The package carrier as claimed in claim 1, further comprising:

a second conductive pattern, disposed adjacent to a second surface of the dielectric layer and including a plurality of second pads, wherein the second via segment of each conductive via is connected to at least one of the second pads.

6. The package carrier as claimed in claim 5, further comprising:

a chip pad support, extending through the dielectric layer,

wherein the first conductive pattern includes a third pad corresponding to a chip pad, and the chip pad support includes a first support segment, connected to the chip pad, and a second support segment, connected to the first support segment.

7. The package carrier as claimed in claim 6, wherein the second conductive pattern includes a fourth pad connected to the second support segment, a lateral extent of the first support segment is greater than the lateral extent of the first via segment, and a lateral extent of the second support segment is greater than the lateral extent of the second via segment.

8. The package carrier as claimed in claim 7, wherein the lateral extent of the first support segment is greater than the lateral extent of the second support segment.

9. The package carrier as claimed in claim 1, further comprising:

a chip pad support, extending through the dielectric layer,

wherein the first conductive pattern includes a chip pad, and the chip pad support includes a first support segment, connected to the chip pad, and a second support segment, connected to the first support segment.

10. A semiconductor package, comprising:

a package carrier, including;

a dielectric layer;

a top conductive pattern, disposed adjacent to a top surface of the dielectric layer, and including a plurality of first pads;

a bottom conductive pattern, disposed adjacent to a bottom surface of the dielectric layer, and including a plurality of second pads; and

a plurality of conductive vias within the dielectric layer and extending between the top conductive pattern and the bottom conductive pattern, wherein each conductive via includes a first segment, connected to at least one of the first pads, and a second segment, connected to at least one of the second pads; and

a chip, attached to the package carrier and connected to the first pads.

11. The semiconductor package as claimed in claim 10, wherein the top conductive pattern is embedded in the dielectric layer.

12. The semiconductor package as claimed in claim 10, wherein a lateral extent of the first segment is greater than a lateral extent of the second segment.

13. The semiconductor package as claimed in claim 10, wherein the conductive vias provide a locking mechanism with respect to the dielectric layer.

14. The semiconductor package as claimed in claim 10, wherein a top surface of the top conductive pattern is aligned with the top surface of the dielectric layer.

15. The semiconductor package as claimed in claim 10, wherein the package carrier further includes:

a chip pad support, extending through the dielectric layer,

wherein the top conductive pattern includes a third pad corresponding to a chip pad, the chip is disposed adjacent to the chip pad, the chip pad support includes a third segment, connected to the chip pad, and a fourth segment, connected to the third segment, the bottom conductive pattern includes a fourth pad connected to the fourth segment, a lateral extent of the third segment is greater than a lateral extent of the first segment, and a lateral extent of the fourth segment is greater than a lateral extent of the second segment.

16. The semiconductor package as claimed in claim 15, further comprising:

at least one conductive bump, disposed adjacent to the fourth pad.

17. The semiconductor package as claimed in claim 10, wherein the package carrier further includes:

an etching stop layer, disposed between the conductive vias and the top conductive pattern.

18. The semiconductor package as claimed in claim 10, wherein the conductive vias correspond to conductive posts.

19. A semiconductor fabrication process, comprising:

forming a first conductive pattern including a plurality of first pads;

forming a plurality of first via segments on at least some of the first pads;

providing a dielectric layer having a plurality of first openings corresponding to the first via segments;

applying the dielectric layer to the first conductive pattern and the first via segments;

forming a plurality of second openings in the dielectric layer, such that the first via segments are exposed by the second openings; and

forming a plurality of second via segments on the first via segments and at least partially within the second openings, such that a diameter of the first via segment is different than a diameter of the second via segment.

20. The process as claimed in claim 19, further comprising:

forming a second conductive pattern including a plurality of second pads, wherein the second via segments are connected to at least some of the second pads.