Chip Having A Metal Pillar Structure

• US 20110084381A1
• Filed: 08/13/2010
• Published: 04/14/2011
• Est. Priority Date: 10/14/2009
• Status: Active Grant

• Current Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Original Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Inventors: Chen, Chien-Fan, Lo, Jian-Wen
• Granted Patent: US 8,334,594 B2
• Time in Patent Office: Days
• US Class Current: 257/737
• CPC Class Codes: H01L 2224/0361 Physical or chemical etching
• CPC Class Codes: H01L 2224/03912 the bump being used as a mask for patterning the bonding area
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05022 the internal layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05027 the internal layer extending out of an opening
• CPC Class Codes: H01L 2224/05099 Material
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05556 in side view
• CPC Class Codes: H01L 2224/05558 conformal layer on a patterned surface
• CPC Class Codes: H01L 2224/05562 On the entire exposed surface of the internal layer
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/0558 being stacked
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05666 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05672 Vanadium [V] as principal constituent
• CPC Class Codes: H01L 2224/1147 using a lift-off mask
• CPC Class Codes: H01L 2224/11849 Reflowing
• CPC Class Codes: H01L 2224/11902 : Multiple masking steps
• CPC Class Codes: H01L 2224/11912 : the bump being used as a mask for patterning other parts
• CPC Class Codes: H01L 2224/13082 : Two-layer arrangements
• CPC Class Codes: H01L 2224/13083 : Three-layer arrangements
• CPC Class Codes: H01L 2224/13099 : Material
• CPC Class Codes: H01L 2224/131 : with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13147 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13155 : Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/13599 : Material
• CPC Class Codes: H01L 2224/141 : Disposition
• CPC Class Codes: H01L 2224/29099 : Material
• CPC Class Codes: H01L 2224/29599 : Material
• CPC Class Codes: H01L 23/3192 : Multilayer coating
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00013 : Fully indexed content
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01327 : Intermediate phases, i.e. intermetallics compounds
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/381 : Pitch distance

Abstract

The present invention relates to a chip having a metal pillar structure. The chip includes a chip body, at least one chip pad, a first passivation layer, an under ball metal layer and at least one metal pillar structure. The chip body has an active surface. The chip pad is disposed on the active surface. The first passivation layer is disposed on the active surface, and has at least one first opening so as to expose part of the chip pad. The under ball metal layer is disposed on the chip pad. The metal pillar structure is disposed on the under ball metal layer, and includes a metal pillar and a solder. The metal pillar is disposed on the under ball metal layer. The solder is disposed on the metal pillar, and the maximum diameter formed by the solder is shorter than or equal to the diameter of the metal pillar. Therefore, when the pitch between two adjacent metal pillar structures of the chip is a fine pitch, the defect of solder bridge can be avoided, so that the yield rate is improved.

Claims

1. A chip having a metal pillar structure, comprising:

a chip body, having an active surface;

at least one chip pad, disposed on the active surface;

a first passivation layer, disposed on the active surface, and having at least one first opening so as to expose part of the chip pad;

an under ball metal layer (UBM), disposed on the chip pad; and

at least one metal pillar structure, disposed on the under ball metal layer (UBM), comprising;

a metal pillar, disposed on the under ball metal layer (UBM); and

a solder, disposed on the metal pillar, wherein the maximum diameter formed by the solder is shorter than or equal to the diameter of the metal pillar.

2. The chip as claimed in claim 1, wherein the under ball metal layer (UBM) is a multi-layered structure.

3. The chip as claimed in claim 1, wherein the distance between the central axes of two adjacent metal pillar structures is defined as a pitch, and the pitch is less than or equal to 150μ

m.

4. The chip as claimed in claim 1, wherein the metal pillar structure further comprises a barrier layer disposed on the metal pillar, and the solder is disposed on the barrier layer.

5. The chip as claimed in claim 1, wherein the peripheral surface of the metal pillar is aligned with the peripheral surface of the under ball metal layer (UBM).

6. The chip as claimed in claim 1, wherein the height of the solder is shorter than or equal to the radius of the metal pillar.

7. The chip as claimed in claim 1, wherein the solder is a hemisphere.

8. The chip as claimed in claim 1, further comprising a second passivation layer, wherein the second passivation layer is disposed on the first passivation layer and has at least one second opening so as to expose part of the chip pad.

9. The chip as claimed in claim 8, wherein the second opening of the second passivation layer is smaller than the first opening of the first passivation layer.

10. The chip as claimed in claim 8, wherein the second opening of the second passivation layer is larger than the first opening of the first passivation layer, and the second opening further exposes part of the first passivation layer.

11. A chip having a metal pillar structure, comprising:

a chip body, having an active surface;

at least one chip pad, disposed on the active surface;

a first passivation layer, disposed on the active surface, and having at least one first opening so as to expose part of the chip pad;

an under ball metal layer (UBM), disposed on the chip pad; and

at least one metal pillar structure, disposed on the under ball metal layer (UBM), comprising;

a metal pillar, disposed on the under ball metal layer (UBM), and having a peripheral surface; and

a solder, disposed in a phantom zone extending upward from the peripheral surface of the metal pillar.

12. The chip as claimed in claim 11, wherein the under ball metal layer (UBM) is a multi-layered structure.

13. The chip as claimed in claim 11, wherein the distance between the central axes of two adjacent metal pillar structures is defined as a pitch, and the pitch is less than or equal to 150 μ

m.

14. The chip as claimed in claim 11, wherein the metal pillar structure further comprises a barrier layer disposed on the metal pillar, the material of the barrier layer is nickel (Ni), and the solder is disposed on the barrier layer.

15. The chip as claimed in Claim 11, wherein the peripheral surface of the metal pillar is aligned with the peripheral surface of the under ball metal layer (UBM), and the material of the metal pillar is copper (Cu).

16. The chip as claimed in claim 11, wherein the height of the solder is shorter than or equal to the radius of the metal pillar.

17. The chip as claimed in claim 11, wherein the solder is a hemisphere.

18. The chip as claimed in claim 11, further comprising a second passivation layer, wherein the second passivation layer is disposed on the first passivation layer, and has at least one second opening so as to expose part of the chip pad, and the material of the second passivation layer is polyimide (PI).

19. The chip as claimed in claim 18, wherein the second opening of the second passivation layer is smaller than the first opening of the first passivation layer.

20. The chip as claimed in claim 18, wherein the second opening of the second passivation layer is larger than the first opening of the first passivation layer, and the second opening further exposes part of the first passivation layer.