DIMMER DECODER WITH LOW DUTY CYCLE HANDLING FOR USE WITH LED DRIVERS

• US 20110084622A1
• Filed: 10/14/2010
• Published: 04/14/2011
• Est. Priority Date: 10/14/2009
• Status: Active Grant

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Nederbragt, Irwin R., Masson, James H., Barrow, Steven M.
• Granted Patent: US 8,947,010 B2
• Time in Patent Office: Days
• US Class Current: 315/250
• CPC Class Codes: H05B 45/10 Controlling the intensity of the light
• CPC Class Codes: H05B 45/375 using buck topology
• CPC Class Codes: H05B 45/385 using flyback topology
• CPC Class Codes: Y02B 20/30 Semiconductor lamps, e.g. solid state lamps [SSL] light emitting diodes [LED] or organic LED [OLED]

Abstract

A method includes receiving a sense signal having multiple pulses, where the sense signal is based on an output of a dimmer. The method also includes, for each of multiple sampling periods, (i) identifying a pulse duty cycle by sampling at least one pulse in the sense signal and calculating a duty cycle of the at least one pulse and (ii) generating an output value identifying a duty cycle for driving one or more LEDs. The output value is based on the pulse duty cycle. The method further includes generating a holding current for the dimmer (i) during the sampling of the at least one pulse in at least one of the sampling periods and (ii) when the pulse duty cycle is less than a specified threshold. The holding current can be applied continuously when the pulse duty cycle is less than the specified threshold (such as 15%).

Claims

1. A method comprising:

receiving a sense signal comprised of multiple pulses, the sense signal based on an output of a dimmer;

for each of multiple sampling periods;

identifying a pulse duty cycle by sampling at least one pulse in the sense signal during that sampling period and calculating a duty cycle of the at least one pulse; and

generating an output value identifying a duty cycle for driving one or more light emitting diodes (LEDs), the output value based on the pulse duty cycle; and

generating a holding current for the dimmer (i) during the sampling of the at least one pulse in at least one of the sampling periods and (ii) when the pulse duty cycle is less than a specified threshold.

2. The method of claim 1, wherein the holding current generated when the pulse duty cycle is less than the specified threshold reduces a likelihood that the dimmer turns off prematurely.

3. The method of claim 1, wherein the holding current is applied continuously when the pulse duty cycle is less than the specified threshold.

4. The method of claim 1, wherein the specified threshold comprises a 15% duty cycle.

5. The method of claim 1, wherein identifying the pulse duty cycle comprises, during each of the sampling periods:

determining duty cycles of multiple pulses in the sense signal during that sampling period;

selecting one of the determined duty cycles;

shifting the selected duty cycle by a specified amount; and

saturating the shifted duty cycle at a minimum value greater than zero, the pulse duty cycle comprising the shifted and saturated duty cycle.

6. The method of claim 5, wherein:

if the shifted duty cycle equals zero, the pulse duty cycle equals zero;

if the shifted duty cycle is greater than the minimum value, the pulse duty cycle equals the shifted duty cycle; and

if the shifted duty cycle is greater than zero and less than the minimum value, the pulse duty cycle equals the minimum value.

7. The method of claim 5, wherein the saturation prevents an increase or decrease of one in the pulse duty cycle from causing a change in LED illumination that exceeds a maximum change.

8. The method of claim 7, wherein:

the minimum value equals six; and

the maximum change comprises a change in LED illumination of 16.7%.

9. A system comprising:

a driver configured to generate a drive signal for controlling illumination from one or more light emitting diode (LEDs); and

a dimmer decoder configured to;

receive a sense signal comprised of multiple pulses, the sense signal based on an output of a dimmer;

for each of multiple sampling periods;

identify a pulse duty cycle by sampling at least one pulse in the sense signal during that sampling period and calculating a duty cycle of the at least one pulse; and

generate an output value identifying a duty cycle for driving the one or more LEDs, the output value based on the pulse duty cycle; and

generate a holding current for the dimmer (i) during the sampling of the at least one pulse in at least one of the sampling periods and (ii) when the pulse duty cycle is less than a specified threshold.

10. The system of claim 9, wherein the dimmer decoder is configured to reduce a likelihood that the dimmer turns off prematurely by generating the holding current when the pulse duty cycle is less than the specified threshold.

11. The system of claim 9, wherein the dimmer decoder is configured to apply the holding current continuously when the pulse duty cycle is less than the specified threshold.

12. The system of claim 11, wherein the specified threshold comprises a 15% duty cycle.

13. The system of claim 9, wherein the dimmer decoder is configured to identify the pulse duty cycle by, during each of the sampling periods:

determining duty cycles of multiple pulses in the sense signal during that sampling period;

selecting one of the determined duty cycles;

shifting the selected duty cycle by a specified amount; and

saturating the shifted duty cycle at a minimum value greater than zero, the pulse duty cycle comprising the shifted and saturated duty cycle.

14. The system of claim 13, wherein:

if the shifted duty cycle equals zero, the pulse duty cycle equals zero;

if the shifted duty cycle is greater than the minimum value, the pulse duty cycle equals the shifted duty cycle; and

if the shifted duty cycle is greater than zero and less than the minimum value, the pulse duty cycle equals the minimum value.

15. The system of claim 13, wherein the dimmer decoder is configured to perform the saturation to prevent an increase or decrease of one in the pulse duty cycle from causing a change in LED illumination that exceeds a maximum change.

16. An apparatus comprising:

a digital block configured to;

receive a sense signal comprised of multiple pulses, the sense signal based on an output of a dimmer;

for each of multiple sampling periods;

identify a pulse duty cycle by sampling at least one pulse in the sense signal during that sampling period and calculating a duty cycle of the at least one pulse; and

generate an output value identifying a duty cycle for driving one or more light emitting diodes (LEDs), the output value based on the pulse duty cycle; and

a dynamic hold current generation circuit configured to generate a holding current for the dimmer (i) during the sampling of the at least one pulse in at least one of the sampling periods and (ii) when the pulse duty cycle is less than a specified threshold.

17. The apparatus of claim 16, wherein the dynamic hold current generation circuit is configured to reduce a likelihood that the dimmer turns off prematurely by generating the holding current when the pulse duty cycle is less than the specified threshold.

18. The apparatus of claim 16, wherein the dynamic hold current generation circuit is configured to apply the holding current continuously when the pulse duty cycle is less than the specified threshold.

19. The apparatus of claim 18, wherein the specified threshold comprises a 15% duty cycle.

20. The apparatus of claim 16, wherein the digital block is configured to identify the pulse duty cycle by, during each of the sampling periods:

determining duty cycles of multiple pulses in the sense signal during that sampling period;

selecting one of the determined duty cycles;

shifting the selected duty cycle by a specified amount; and

saturating the shifted duty cycle at a minimum value greater than zero, the pulse duty cycle comprising the shifted and saturated duty cycle, the shifted duty cycle saturated such that the pulse duty cycle cannot have a value greater than zero and less than the minimum value.