SHIFT REGISTER AND DISPLAY DEVICE AND DRIVING METHOD THEREOF

• US 20110085635A1
• Filed: 10/04/2010
• Published: 04/14/2011
• Est. Priority Date: 10/09/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Koyama, Jun
• Granted Patent: US 8,526,567 B2
• Time in Patent Office: Days
• US Class Current: 377/78
• CPC Class Codes: G09G 2300/0408 Integration of the drivers onto the display substrate
• CPC Class Codes: G09G 2300/0417 Special arrangements specific to the use of low carrier mobility technology
• CPC Class Codes: G09G 2310/0267 Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
• CPC Class Codes: G09G 2330/021 Power management, e.g. power saving
• CPC Class Codes: G09G 3/3266 Details of drivers for scan electrodes
• CPC Class Codes: G09G 3/3677 suitable for active matrices only
• CPC Class Codes: G11C 19/28 using semiconductor elements G11C19/14, G11C19/36 take precedence
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO

Abstract

The power consumption of a shift register or a display device including the shift register is reduced. A clock signal is supplied to a shift register by a plurality of wirings, not by one wiring. Any one of the plurality of wirings supplies a clock signal in only part of the operation period of the shift register, not during the whole operation period of the shift register. Therefore, the capacity load caused with the supply of clock signals can be reduced, leading to reduction in power consumption of the shift register.

Claims

1. A driving method of a shift register comprising a first line, a second line, a third line, a fourth line, a first flip-flop, a second flip-flop, a third flip-flop, and a fourth flip-flop, the driving method comprising:

supplying a clock signal to the first flip-flop from the first line and supplying a start pulse to the first flip-flop during a first period;

supplying a clock signal to the second flip-flop from the second line during a second period;

supplying an inverted clock signal to the third flip-flop from the third line and supplying a first signal to the third flip-flop from the first flip-flop during a third period; and

supplying an inverted clock signal to the fourth flip-flop from the fourth line and supplying a second signal to the fourth flip-flop from the second flip-flop during a fourth period,

wherein the third period overlaps with the first period, and the fourth period overlaps with the second period, and

wherein both the first signal and the second signal have a high-level potential.

2. The driving method of a shift register according to claim 1,

wherein the first line supplies a low power supply potential during a period except the first period,

wherein the second line supplies a low power supply potential during a period except the second period,

wherein the third line supplies a low power supply potential during a period except the third period, and

wherein the fourth line supplies a low power supply potential during a period except the fourth period.

3. The driving method of a shift register according to claim 1,

wherein the first flip-flop comprises a transistor including an oxide semiconductor film.

4. The driving method of a shift register according to claim 1,

wherein the first flip-flop comprises a first transistor and a second transistor,

wherein a first terminal of the first transistor is electrically connected to the first line, and a second terminal of the first transistor is electrically connected to an output terminal of the first flip-flop,

wherein a first terminal of the second transistor is electrically connected to the second terminal of the first transistor and the output terminal of the first flip-flop, a second terminal of the second transistor is electrically connected to a wiring for supplying a low power supply potential, and

wherein each of the first transistor and the second transistor comprises an oxide semiconductor film.

5. The driving method of a shift register according to claim 1,

wherein the first flip-flop comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor,

wherein a first terminal of the third transistor is electrically connected to a wiring for supplying a high power supply potential,

wherein a first terminal of the fourth transistor is electrically connected to the second terminal of the first transistor, a second terminal of the fourth transistor is electrically connected to a wiring for supplying a low power supply potential,

wherein a first terminal of the fifth transistor is electrically connected to a wiring for supplying a high power supply potential,

wherein a gate terminal of the sixth transistor is electrically connected to a second terminal of the third transistor and the first terminal of the fourth transistor, a first terminal of the sixth transistor is electrically connected to the second terminal of the fifth transistor, and a second terminal of the sixth transistor is electrically connected to a wiring for supplying a low power supply potential,

wherein a gate terminal of the first transistor is electrically connected to the second terminal of the fifth transistor and the first terminal of the sixth transistor, a first terminal of the first transistor is electrically connected to the first line, and the second terminal of the first transistor is electrically connected to the output terminal of the first flip-flop,

wherein a gate terminal of the second transistor is electrically connected to the second terminal of the third transistor, the first terminal of the fourth transistor, and the gate terminal of the sixth transistor,

wherein a first terminal of the second transistor is electrically connected to the second terminal of the first transistor and the output terminal of the first flip-flop, and the second terminal of the second transistor is electrically connected to a wiring for supplying a low power supply potential, and

wherein each of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor comprises an oxide semiconductor film.

6. The driving method of a shift register according to claim 1,

wherein the shift register comprises:

a seventh transistor in which a first terminal is electrically connected to the first line and a second terminal is electrically connected to a reference clock signal line, the seventh transistor being kept on during the first period;

an eighth transistor in which a first terminal is electrically connected to the second line and a second terminal is electrically connected to the reference clock signal line, the eighth transistor being kept on during the second period;

a ninth transistor in which a first terminal is electrically connected to the third line and a second terminal is electrically connected to an inverted reference clock signal line, the ninth transistor being kept on during the third period; and

a tenth transistor in which a first terminal is electrically connected to the fourth line and a second terminal is electrically connected to the inverted reference clock signal line, the tenth transistor being kept on during the fourth period.

7. The driving method of a shift register according to claim 1,

wherein the shift register comprises:

an eleventh transistor in which a first terminal is electrically connected to the first line and a second terminal is electrically connected to a wiring for supplying a low power supply potential, the eleventh transistor being kept on during a period except the first period;

a twelfth transistor in which a first terminal is electrically connected to the second line and a second terminal is electrically connected to a wiring for supplying a low power supply potential, the twelfth transistor being kept on during a period except the second period;

a thirteenth transistor in which a first terminal is electrically connected to the third line and a second terminal is electrically connected to the wiring for supplying a low power supply potential, the thirteenth transistor being kept on during a period except the third period; and

a fourteenth transistor in which a first terminal is electrically connected to the fourth line and a second terminal is electrically connected to the wiring for supplying a low power supply potential, the fourteenth transistor being kept on during a period except the fourth period.

8. A shift register comprising:

a first line;

a second line;

a third line;

a fourth line;

a first flip-flop;

a second flip-flop;

a third flip-flop; and

a fourth flip-flop,

wherein the first line is configured to supply a clock signal,

wherein the second line is configured to supply an inverted clock signal,

wherein the third line is configured to supply a clock signal,

wherein the fourth line is configured to supply an inverted clock signal,

wherein the first flip-flop is electrically connected to the first line,

wherein an output terminal of the first flip-flop is electrically connected to an input terminal of the second flip-flop,

wherein the second flip-flop is electrically connected to the second line,

wherein the third flip-flop is electrically connected to the third line,

wherein the output terminal of the third flip-flop is electrically connected to an input terminal of the fourth flip-flop, and

wherein the fourth flip-flop is electrically connected to the fourth line.

9. The shift register according to claim 8,

wherein the first flip-flop comprises a transistor including an oxide semiconductor film.

10. The shift register according to claim 8,

wherein the first flip-flop comprises a first transistor and a second transistor,

wherein a first terminal of the first transistor is electrically connected to the first line, a second terminal of the first transistor is electrically connected to the output terminal of the first flip-flop,

wherein a first terminal of the second transistor is electrically connected to the second terminal of the first transistor and the output terminal of the first flip-flop, a second terminal of the second transistor is electrically connected to a wiring for supplying a low power supply potential, and

wherein each of the first transistor and the second transistor comprises an oxide semiconductor film.

11. The shift register according to claim 8,

wherein the first flip-flop comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor,

wherein a first terminal of the third transistor is electrically connected to a wiring for supplying a high power supply potential,

wherein a first terminal of the fourth transistor is electrically connected to the second terminal of the first transistor, a second terminal of the fourth transistor is electrically connected to a wiring for supplying a low power supply potential,

wherein a first terminal of the fifth transistor is electrically connected to a wiring for supplying a high power supply potential,

wherein a gate terminal of the sixth transistor is electrically connected to a second terminal of the third transistor and the first terminal of the fourth transistor, a first terminal of the sixth transistor is electrically connected to the second terminal of the fifth transistor, a second terminal of the sixth transistor is electrically connected to a wiring for supplying a low power supply potential,

wherein a gate terminal of the first transistor is electrically connected to the second terminal of the fifth transistor and the first terminal of the sixth transistor, a first terminal of the first transistor is electrically connected to the first line, and the second terminal of the first transistor is electrically connected to the output terminal of the first flip-flop,

wherein a gate terminal of the second transistor is electrically connected to the second terminal of the third transistor, the first terminal of the fourth transistor, and the gate terminal of the sixth transistor,

wherein a first terminal of the second transistor is electrically connected to the second terminal of the first transistor and the output terminal of the first flip-flop, and the second terminal of the second transistor is electrically connected to a wiring for supplying a low power supply potential, and

wherein each of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor comprises an oxide semiconductor film.

12. The shift register according to claim 8, further comprising:

a seventh transistor;

an eighth transistor;

a ninth transistor; and

a tenth transistor,

wherein a first terminal of the seventh transistor is electrically connected to the first line and a second terminal of the seventh transistor is electrically connected to a reference clock signal line,

wherein a first terminal of the eighth transistor is electrically connected to the third line and a second terminal of the eighth transistor is electrically connected to the reference clock signal line,

wherein a first terminal of the ninth transistor is electrically connected to the second line and a second terminal of the ninth transistor is electrically connected to an inverted reference clock signal line, and

wherein a first terminal of the tenth transistor is electrically connected to the fourth line and a second terminal of the tenth transistor is electrically connected to the inverted reference clock signal line.

13. The shift register according to claim 8, further comprising:

an eleventh transistor;

a twelfth transistor;

a thirteenth transistor;

a fourteenth transistor;

wherein a first terminal of the eleventh transistor is electrically connected to the first line and a second terminal of the eleventh transistor is electrically connected to a wiring for supplying a low power supply potential,

wherein a first terminal of the twelfth transistor is electrically connected to the third line and a second terminal of the twelfth transistor is electrically connected to the wiring for supplying a low power supply potential,

wherein a first terminal of the thirteenth transistor is electrically connected to the second line and a second terminal of the thirteenth transistor is electrically connected to the wiring for supplying a low power supply potential, and

wherein a first terminal of the fourteenth transistor is electrically connected to the fourth line and a second terminal of the fourteenth transistor is electrically connected to the wiring for supplying a low power supply potential.

14. A display device comprising the shift register according to claim 8.

15. A shift register comprising:

a first line;

a second line;

a third line;

a fourth line;

a first flip-flop;

a second flip-flop;

a third flip-flop;

a fourth flip-flop;

a fifth flip-flop; and

a sixth flip-flop,

wherein the first line is configured to supply a clock signal,

wherein the second line is configured to supply an inverted clock signal,

wherein the third line is configured to supply a clock signal,

wherein the fourth line is configured to supply an inverted clock signal,

wherein the first flip-flop is electrically connected to the first line,

wherein an output terminal of the first flip-flop is electrically connected to an input terminal of the second flip-flop,

wherein the second flip-flop is electrically connected to the second line,

wherein an output terminal of the second flip-flop is electrically connected to an input terminal of the third flip-flop,

wherein the third flip-flop is electrically connected to the first line,

wherein an output terminal of the third flip-flop is electrically connected to an input terminal of the fourth flip-flop,

wherein the fourth flip-flop is electrically connected to the second line,

wherein an output terminal of the fourth flip-flop is electrically connected to an input terminal of the fifth flip-flop,

wherein the fifth flip-flop is electrically connected to the third line,

wherein the output terminal of the fifth flip-flop is electrically connected to an input terminal of the sixth flip-flop, and

wherein the sixth flip-flop is electrically connected to the fourth line.

16. The shift register according to claim 15,

wherein the first flip-flop comprises a transistor including an oxide semiconductor film.

17. The shift register according to claim 15,

wherein the first flip-flop comprises a first transistor and a second transistor,

wherein a first terminal of the first transistor is electrically connected to the first line, and a second terminal of the first transistor is electrically connected to an output terminal of the first flip-flop,

wherein a first terminal of the second transistor is electrically connected to the second terminal of the first transistor and the output terminal of the first flip-flop, and a second terminal of the second transistor is electrically connected to a wiring for supplying a low power supply potential, and

wherein each of the first transistor and the second transistor comprises an oxide semiconductor film.

18. The shift register according to claim 15,

wherein the first flip-flop comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor,

wherein a first terminal of the third transistor is electrically connected to a wiring for supplying a high power supply potential,

wherein a first terminal of the fourth transistor is electrically connected to the second terminal of the first transistor, and a second terminal of the fourth transistor is electrically connected to a wiring for supplying a low power supply potential,

wherein a first terminal of the fifth transistor is electrically connected to a wiring for supplying a high power supply potential,

wherein a gate terminal of the sixth transistor is electrically connected to a second terminal of the third transistor and the first terminal of the fourth transistor, a first terminal of the sixth transistor is electrically connected to the second terminal of the fifth transistor, and a second terminal of the sixth transistor is electrically connected to a wiring for supplying a low power supply potential,

wherein a gate terminal of the first transistor is electrically connected to the second terminal of the fifth transistor and the first terminal of the sixth transistor, a first terminal of the first transistor is electrically connected to the first line, and the second terminal of the first transistor is electrically connected to the output terminal of the first flip-flop,

wherein a gate terminal of the second transistor is electrically connected to the second terminal of the third transistor, the first terminal of the fourth transistor, and the gate terminal of the sixth transistor,

wherein a first terminal of the second transistor is electrically connected to the second terminal of the first transistor and the output terminal of the first flip-flop, and the second terminal of the second transistor is electrically connected to a wiring for supplying a low power supply potential, and

wherein each of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor comprises an oxide semiconductor film.

19. The shift register according to claim 15, further comprising:

a seventh transistor;

an eighth transistor;

a ninth transistor; and

a tenth transistor,

wherein a first terminal of the seventh transistor is electrically connected to the first line and a second terminal of the seventh transistor is electrically connected to a reference clock signal line,

wherein a first terminal of the eighth transistor is electrically connected to the third line and a second terminal of the eighth transistor is electrically connected to the reference clock signal line,

wherein a first terminal of the ninth transistor is electrically connected to the second line and a second terminal of the ninth transistor is electrically connected to an inverted reference clock signal line, and

wherein a first terminal of the tenth transistor is electrically connected to the fourth line and a second terminal of the tenth transistor is electrically connected to the inverted reference clock signal line.

20. The shift register according to claim 15, further comprising:

an eleventh transistor;

a twelfth transistor;

a thirteenth transistor;

a fourteenth transistor;

wherein a first terminal of the eleventh transistor is electrically connected to the first line and a second terminal of the eleventh transistor is electrically connected to a wiring for supplying a low power supply potential,

wherein a first terminal of the twelfth transistor is electrically connected to the third line and a second terminal of the twelfth transistor is electrically connected to the wiring for supplying a low power supply potential,

wherein a first terminal of the thirteenth transistor is electrically connected to the second line and a second terminal of the thirteenth transistor is electrically connected to the wiring for supplying a low power supply potential, and

wherein a first terminal of the fourteenth transistor is electrically connected to the fourth line and a second terminal of the fourteenth transistor is electrically connected to the wiring for supplying a low power supply potential.

21. A display device comprising the shift register according to claim 15.