Methods of Forming Field Effect Transistors on Substrates
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Accused Products
Abstract
The invention includes methods of forming field effect transistors. In one implementation, the invention encompasses a method of forming a field effect transistor on a substrate, where the field effect transistor comprises a pair of conductively doped source/drain regions, a channel region received intermediate the pair of source/drain regions, and a transistor gate received operably proximate the channel region. Such implementation includes conducting a dopant activation anneal of the pair of source/drain regions prior to depositing material from which a conductive portion of the transistor gate is made. Other aspects and implementations are contemplated.
105 Citations
54 Claims
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1-13. -13. (canceled)
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14. A method of forming a field effect transistor on a substrate, the field effect transistor comprising a pair of conductively doped source/drain regions, a channel region received intermediate the pair of source/drain regions, and a transistor gate received operably proximate the channel region, the method comprising:
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ion implanting conductivity enhancing impurity dopant into semiconductive material of the substrate to form highest dopant concentration portions of the pair of source/drain regions; conducting a dopant activation anneal of the highest dopant concentration portions of the pair of source/drain regions; and after the dopant activation anneal, depositing material from which a conductive portion of the transistor gate is made. - View Dependent Claims (15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27)
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28. A method of forming a field effect transistor on a substrate, the field effect transistor comprising a pair of conductively doped source/drain regions, a channel region received intermediate the pair of source/drain regions, and a transistor gate received operably proximate the channel region, the method comprising:
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ion implanting conductivity enhancing impurity dopant into an implant region of semiconductive material of the substrate to a highest dopant concentration for the pair of source/drain regions; after the ion implanting, conducting a dopant activation anneal of the implant region; after the dopant activation anneal, etching an opening through the implant region into semiconductive material of the substrate; and forming gate dielectric and conductive material of the transistor gate within the opening. - View Dependent Claims (29, 30, 38, 39)
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31-37. -37. (canceled)
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40. A method of forming an n-channel field effect transistor and a p channel field effect transistor on a substrate, said transistors respectively comprising a pair of conductively doped source/drain regions, a channel region received intermediate the pair of source/drain regions, and a transistor gate received operably proximate the channel region, the method comprising:
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ion implanting p-type conductivity enhancing impurity dopant into semiconductive material of the substrate to form highest dopant concentration portions of the pair of source/drain regions of the p-channel field effect transistor; ion implanting n-type conductivity enhancing impurity dopant into semiconductive material of the substrate to form highest dopant concentration portions of the pair of source/drain regions of the n-channel field effect transistor; simultaneously conducting a dopant activation anneal of the highest dopant concentration portions of the pair of source/drain regions of each of the n-channel field effect transistor and of the p-channel field effect transistor; and after the dopant activation anneal, depositing material from which conductive portions of the transistor gates are made. - View Dependent Claims (41, 42)
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43-48. -48. (canceled)
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49. A method of forming an n-channel field effect transistor and a p channel field effect transistor on a substrate, said transistors respectively comprising a pair of conductively doped source/drain regions, a channel region received intermediate the pair of source/drain regions, and a transistor gate received operably proximate the channel region, the method comprising:
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ion implanting p-type conductivity enhancing impurity dopant into a first region of semiconductive material of the substrate to a highest dopant concentration for the pair of source/drain regions of the p-channel field effect transistor; ion implanting n-type conductivity enhancing impurity dopant into a second region of semiconductive material of the substrate to a highest dopant concentration for the pair of source/drain regions of the n-channel field effect transistor; simultaneously conducting a dopant activation anneal of the first and second regions; after the dopant activation anneal, etching a first opening through the first region into semiconductive material of the substrate and etching a second opening through the second region into semiconductive material of the substrate; forming gate dielectric within the first and second openings; and forming conductive material of the transistor gate of the p-channel field effect transistor over the gate dielectric within the first opening and conductive material of the transistor gate of the n-channel field effect transistor over the gate dielectric within the second opening. - View Dependent Claims (53, 54)
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50-52. -52. (canceled)
Specification