SEMICONDUCTOR CHIP HAVING ISLAND DISPERSION STRUCTURE AND METHOD FOR MANUFACTURING THE SAME

• US 20110086493A1
• Filed: 12/17/2010
• Published: 04/14/2011
• Est. Priority Date: 11/30/2005
• Status: Active Grant

• Current Assignee: Longitude Licensing Limited (Vector Capital Corporation)
• Original Assignee: Elpida Memory Incorporated (Micron Technology, Inc.)
• Inventors: Aoki, Shigeru, Oyu, Kiyonori
• Granted Patent: US 8,088,673 B2
• Time in Patent Office: Days
• US Class Current: 438/460
• CPC Class Codes: H01L 21/306 Chemical or electrical treatment, e.g. electrolytic etching to form insulating layers H01L21/31
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 21/308 using masks H01L21/3063, H01L21/3065 take precedence
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 23/26 including materials for absorbing or reacting with moisture or other undesired substances , e.g. getters
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/562 Protection against mechanical damage H01L23/02, H01L23/28 take precedence
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The present invention has an object to provide a semiconductor chip of high reliability with less risk of breakage. Specifically, the present invention provides a semiconductor chip having a semiconductor silicon substrate including a semiconductor device layer and a porous silicon domain layer, the semiconductor device layer being provided in a main surface region on one surface of the semiconductor silicon substrate, the porous silicon domain layer being provided in a main surface region on a back surface which is the other surface of the semiconductor silicon substrate, and the porous silicon domain layer having porous silicon domains dispersed like islands in the back surface of the semiconductor silicon substrate.

Claims

1-20. -20. (canceled)

21. A method for manufacturing a semiconductor chip comprising the steps of:

(1) forming a semiconductor device layer in a main surface region on one surface of a semiconductor silicon wafer;

(2) grinding a back surface which is another surface of the semiconductor silicon wafer up to a predetermined thickness after the step (1);

(3) forming a porous silicon domain layer in the back surface of the semiconductor silicon wafer after the step (2); and

(4) dicing a worked semiconductor wafer obtained through the steps (1) to (3), and

the step (3) including bringing a mixed vapor generated from a mixed liquid of hydrofluoric acid and nitric acid into contact with the back surface of the semiconductor silicon wafer.

22. The method of claim 21,

wherein the mixed vapor generated from the mixed liquid of hydrofluoric acid and nitric acid is a mixed vapor generated from a mixed liquid of 49% hydrofluoric acid solution and concentrated nitric acid, and

a mixture ratio of the mixed liquid of 49% hydrofluoric acid solution and

concentrated nitric acid ranges from 1:

1 to 1;

100 on the basis of volumes before mixing.

23. The method of claim 21,

wherein temperature of the mixed liquid ranges from 30 to 60°

C. when the mixed vapor is generated from the mixed liquid.

24. The method of claim 21,

wherein when the back surface of the semiconductor silicon wafer is brought in contact with the mixed vapor, the back surface of the semiconductor silicon wafer and the mixed vapor are irradiated with light.

25. The method of claim 21,

wherein in the step (2), the predetermined thickness ranges from 50 to 300 μ

m.

26. The method of claim 21, further comprising, between the steps (3) and (4), the step of (5) removing porous silicon domains from the porous silicon domain layer formed on the back surface of the semiconductor silicon wafer.

27. The method of claim 26, further comprising, between the steps (5) and (4), the step of forming a porous silicon layer on the back surface of the semiconductor silicon wafer.

28. The method of claim 21, further comprising, between the steps (3) and (4), the step of forming a porous silicon layer on the back surface of the semiconductor silicon wafer.

29. The method of claim 27,

wherein the porous silicon layer is formed by acting a mixed liquid of 49% hydrofluoric acid solution and concentrated nitric acid on the back surface of the semiconductor silicon wafer as a stain etching method.

30. The method of claim 28,

wherein the porous silicon layer is formed by acting a mixed liquid of 49% hydrofluoric acid solution and concentrated nitric acid on the back surface of the semiconductor silicon wafer as a stain etching method.

31. The method of claim 29,

wherein a volume of the concentrated nitric acid before mixing is less than a volume of the 49% hydrofluoric acid solution in the mixed liquid of 49% hydrofluoric acid solution and concentrated nitric acid.

32. The method of claim 30,

wherein a volume of the concentrated nitric acid before mixing is less than a volume of the 49% hydrofluoric acid solution in the mixed liquid of 49% hydrofluoric acid solution and the concentrated nitric acid.

33. The method of claim 29,

wherein temperature of the mixed liquid of 49% hydrofluoric acid solution and concentrated nitric acid ranges from 0 to 80°

C.

34. The method of claim 30,

wherein temperature of the mixed liquid of 49% hydrofluoric acid solution and concentrated nitric acid ranges from 0 to 80°

C.

35. The method of claim 29,

wherein the porous silicon layer is formed by acting the mixed liquid on the back surface of the semiconductor silicon wafer while the back surface of the semiconductor silicon wafer and the mixed liquid are radiated with light.

36. The method of claim 30,

wherein the porous silicon layer is formed by acting the mixed liquid on the back surface of the semiconductor silicon wafer while the back surface of the semiconductor silicon wafer and the mixed liquid are radiated with light.

37. The method of claim 21,

wherein an average diameter of porous silicon domains appearing in the porous silicon domain layer ranges from 0.2 to 800 μ

m.

38. The method of claim 21,

wherein a total area of porous silicon domains appearing in the porous silicon domain layer ranges from 10 to 90% of a total area of the back surface of the semiconductor silicon substrate.

39. The method of claim 27,

wherein a thickness of the porous silicon layer ranges from 0.01 to 0.2 μ

m.

40. The method of claim 28,

wherein a thickness of the porous silicon layer ranges from 0.01 to 0.2 μ

m.

41. A method for manufacturing a semiconductor chip comprising the steps of:

(i) forming a semiconductor device layer in a main surface region on one surface of a semiconductor silicon wafer;

(ii) grinding a back surface which is another surface of the semiconductor silicon wafer up to a predetermined thickness after the step (i);

(iii) forming a dimple layer in the back surface of the semiconductor silicon wafer after the step (ii); and

(iv) dicing a worked semiconductor wafer obtained through the steps (i) to (iii), and

the step (iii) including performing wet etching and/or dry etching on the back surface of the semiconductor silicon wafer.

42. The method of claim 41, further comprising, between the steps (iii) and (iv), the step of forming a porous silicon layer on the back surface of the semiconductor silicon wafer.

43. The method of claim 42,

wherein a thickness of the porous silicon layer ranges from 0.01 to 0.2 μ

m.

44. The method of claim 41,

wherein an average diameter of dimples in the dimple layer ranges from 0.2 to 800 μ

m.

45. The method of claim 41,

wherein a total area of dimples in the dimple layer ranges from 10 to 90% of a total area of the back surface of the semiconductor silicon substrate.