Method and Apparatus for Protecting Data Using Variable Size Page Stripes in a FLASH-Based Storage System

• US 20110087855A1
• Filed: 12/17/2010
• Published: 04/14/2011
• Est. Priority Date: 08/11/2009
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: Texas Memory Systems Incorporated (International Business Machines Corporation)
• Inventors: Frost, Holloway H., Camp, Charles J., Fuxa, James A.
• Granted Patent: US 8,443,136 B2
• Time in Patent Office: Days
• US Class Current: 711/202
• CPC Class Codes: G06F 11/1016 Error in accessing a memory location, i.e. addressing error
• CPC Class Codes: G06F 11/1044 with specific ECC/EDC distribution
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 11/1076 Parity data used in redundant arrays of independent storages, e.g. in RAID systems
• CPC Class Codes: G06F 11/108 Parity data distribution in semiconductor storages, e.g. in SSD
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/14 Protection against unauthorised use of memory or access to memory
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/0644 Management of space entities, e.g. partitions, extents, pools
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents

Abstract

Methods and apparatuses for enhanced protection of data stored in a FLASH memory system involve a controller capable of using variable size page stripes in the memory system. The controller is configured to store data such that each page stripe comprises a plurality of data pages, with each data page in the page stripe being stored in a different FLASH memory chip. The controller is also configured to maintain one or more buffers containing information reflecting blocks of memory within the FLASH memory chips that have been erased and are available for information storage, and to dynamically determine the number of data pages to be included in a page stripe based on the information in the one or more buffers such that a first page stripe and a second page stripe can have different numbers of data pages.

Claims

1. A memory system comprising:

a plurality of FLASH memory chips, each of the plurality of FLASH memory chips being associated with a plurality of physical memory address locations;

a system controller that includes an external communication bus interface for receiving WRITE requests from an external host device, wherein each WRITE request includes a data item and a logical memory address associated with the data item, the system controller further comprising a plurality of internal communication bus interfaces, each allowing the system controller to write data into physical memory locations associated with one or more of the FLASH memory chips; and

a plurality of internal data communication buses, each internal data communications bus coupling one or more of the FLASH memory chips to an internal communication bus interface of the system controller;

wherein the system controller is configured, for each WRITE request, to translate the logical memory address provided by the external host to a physical memory address and to write the data item provided as part of the WRITE request to the physical memory location corresponding to the physical memory address; and

wherein the system controller is further configured to;

(i) associate a number of data items received through a plurality of WRITE requests with each other to form a group of received data items;

(ii) generate data protection information for each group and write the data protection information to a physical memory location;

(iii) perform the translation of the received logical memory addresses for the data items in the group and select the physical memory location for storage of the data protection information such that each of the data items is stored in a physical memory location within a FLASH memory chip that is different from the FLASH memory chips in which the other data items and the data protection information for the group of received data items are stored; and

(iv) dynamically select the number of data items used to form each group, such that the number of data items in one group of received data items differs from the number of data items in a second group of received data items.

2. The memory system of claim 1 wherein the system controller is configured to dynamically select the number of data items used to form each group based on information reflecting the actual or predicted failure of one or more FLASH memory chips.

3. The memory system of claim 1 wherein the system controller is configured to dynamically select the number of data items used to form each group based on the number of data items received from an external host over a defined time period.

4. The memory system of claim 1 wherein the system controller is configured to dynamically select the number of data items used to form each group based on the number of memory locations with the FLASH memory chips that are available for the storage of data at the time the data items are associated with each other to form the group.

5. The memory system of claim 1 wherein the system controller is configured to dynamically select the number of data items used to form each group based on the presence or absence of a data error associated with a READ operation of a data item.

6. The memory system of claim 1 wherein the system controller is configured to dynamically select the number of data items used such that the maximum number of data items within a group is ten or less.