PERCEPTRON-BASED BRANCH PREDICTION MECHANISM FOR PREDICTING CONDITIONAL BRANCH INSTRUCTIONS ON A MULTITHREADED PROCESSOR
First Claim
1. A multithreaded microprocessor comprising:
- an instruction fetch unit configured to fetch and maintain a plurality of instructions belonging to one or more threads; and
one or more execution units configured to concurrently execute the one or more threads;
wherein the instruction fetch unit includes a conditional branch prediction unit configured to provide, for each of the one or more threads, a direction branch prediction in response to receiving an instruction fetch address of a current conditional branch instruction, wherein the conditional branch prediction unit includes;
a plurality of storages each including a plurality of entries, wherein each entry is configured to store one or more prediction values, and each prediction value of a given storage corresponds to at least one conditional branch instruction in a cache line; and
a control unit coupled to the plurality of storages and configured to generate a separate index value for accessing each storage, wherein the control unit is configured to generate a first index value for accessing a first storage by combining one or more portions of the instruction fetch address, and to generate each other index value for accessing each other respective storage by combining the first index value with a different portion of direction branch history information for each storage.
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Abstract
A multithreaded microprocessor includes an instruction fetch unit including a perceptron-based conditional branch prediction unit configured to provide, for each of one or more concurrently executing threads, a direction branch prediction. The conditional branch prediction unit includes a plurality of storages each including a plurality of entries. Each entry may be configured to store one or more prediction values. Each prediction value of a given storage may correspond to at least one conditional branch instruction in a cache line. The conditional branch prediction unit may generate a separate index value for accessing each storage by generating a first index value for accessing a first storage by combining one or more portions of a received instruction fetch address, and generating each other index value for accessing the other storages by combining the first index value with a different portion of direction branch history information.
25 Citations
20 Claims
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1. A multithreaded microprocessor comprising:
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an instruction fetch unit configured to fetch and maintain a plurality of instructions belonging to one or more threads; and one or more execution units configured to concurrently execute the one or more threads; wherein the instruction fetch unit includes a conditional branch prediction unit configured to provide, for each of the one or more threads, a direction branch prediction in response to receiving an instruction fetch address of a current conditional branch instruction, wherein the conditional branch prediction unit includes; a plurality of storages each including a plurality of entries, wherein each entry is configured to store one or more prediction values, and each prediction value of a given storage corresponds to at least one conditional branch instruction in a cache line; and a control unit coupled to the plurality of storages and configured to generate a separate index value for accessing each storage, wherein the control unit is configured to generate a first index value for accessing a first storage by combining one or more portions of the instruction fetch address, and to generate each other index value for accessing each other respective storage by combining the first index value with a different portion of direction branch history information for each storage. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A method comprising:
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an instruction fetch unit fetching a plurality of instructions belonging to one or more threads; one or more execution units concurrently executing the instructions from the one or more threads; a direction branch prediction unit providing for each of the one or more threads, a direction branch prediction for one or more conditional branch instructions in a cache line in response to receiving an instruction fetch address of a current conditional branch instruction; a control unit storing within each entry of a plurality of storages, one or more prediction values, wherein each prediction value of a given storage corresponds to at least one conditional branch instruction in the cache line; and the control unit generating a separate index value for accessing each storage, wherein the control unit further generating a first index value for accessing a first storage by combining one or more portions of the instruction fetch address, and generating each other index value for accessing each other respective storage by combining the first index value with a different portion of direction branch history information for each storage. - View Dependent Claims (14, 15, 16, 17)
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18. A system comprising:
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a multithreaded processor including a plurality of multithreaded processor cores, wherein each multithreaded processor core includes; an instruction fetch unit configured to fetch and maintain a plurality of instructions belonging to one or more threads; and one or more execution units configured to concurrently execute the one or more threads; wherein the instruction fetch unit includes a conditional branch prediction unit configured to provide for each of the one or more threads, a direction branch prediction for one or more conditional branch instructions in a cache line in response to receiving an instruction fetch address of a current conditional branch instruction, wherein the conditional branch prediction unit includes; a plurality of storages each including a plurality of entries, wherein each entry is configured to store one or more prediction values, and each prediction value of a given storage corresponds to at least one conditional branch instruction in the cache line; and a control unit coupled to the plurality of storages and configured to generate a separate index value for accessing each storage, wherein the control unit is configured to generate a first index value for accessing a first storage by combining one or more portions of the instruction fetch address, and to generate each other index value for accessing each other respective storage by combining the first index value with a different portion of direction branch history information for each storage. - View Dependent Claims (19, 20)
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Specification