APPARATUS AND METHOD FOR LOCAL OPERAND BYPASSING FOR CRYPTOGRAPHIC INSTRUCTIONS

• US 20110087895A1
• Filed: 10/08/2009
• Published: 04/14/2011
• Est. Priority Date: 10/08/2009
• Status: Active Grant

• Current Assignee: Oracle America, Inc. (Oracle Corporation)
• Original Assignee: Oracle America, Inc. (Oracle Corporation)
• Inventors: Olson, Christopher H., Grohoski, Gregory F., Golla, Robert T.
• Granted Patent: US 8,356,185 B2
• Time in Patent Office: Days
• US Class Current: 713/190
• CPC Class Codes: G06F 21/72 in cryptographic circuits
• CPC Class Codes: G06F 9/30007 to perform operations on data operands
• CPC Class Codes: G06F 9/3826 Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage
• CPC Class Codes: G06F 9/3867 using instruction pipelines
• CPC Class Codes: G06F 9/3873 Variable length pipelines, e.g. elastic pipeline
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: G09C 1/00 Apparatus or methods whereby a given sequence of signs, e.g. an intelligible text, is transformed into an unintelligible sequence of signs by transposing the signs or groups of signs or by replacing them by others according to a predetermined system cryptographic typewriters G09C3/00
• CPC Class Codes: H04L 2209/12 Details relating to cryptographic hardware or logic circuitry
• CPC Class Codes: H04L 2209/125 Parallelization or pipelining, e.g. for accelerating processing of cryptographic operations
• CPC Class Codes: H04L 2209/24 Key scheduling, i.e. generating round keys or sub-keys for block encryption
• CPC Class Codes: H04L 9/0637 Modes of operation, e.g. cipher block chaining [CBC], electronic codebook [ECB] or Galois/counter mode [GCM]

Abstract

A processor may include a hardware instruction fetch unit configured to issue instructions for execution, and a hardware functional unit configured to receive instructions for execution, where the instructions include cryptographic instruction(s) and non-cryptographic instruction(s). The functional unit may include a cryptographic execution pipeline configured to execute the cryptographic instructions with a corresponding cryptographic execution latency, and a non-cryptographic execution pipeline configured to execute the non-cryptographic instructions with a corresponding non-cryptographic execution latency that is longer than the cryptographic execution latency. The functional unit may further include a local bypass network configured to bypass results produced by the cryptographic execution pipeline to dependent cryptographic instructions executing within the cryptographic execution pipeline, such that each instruction within a sequence of dependent cryptographic instructions is executable with the cryptographic execution latency, and where the results of the cryptographic execution pipeline are not bypassed to any other functional unit within the processor.

Claims

1. A processor, comprising:

a hardware instruction fetch unit configured to issue instructions for execution, wherein the instructions are programmer-selectable from a defined instruction set architecture (ISA); and

a hardware functional unit configured to receive instructions for execution from the instruction fetch unit, wherein the instructions include one or more cryptographic instructions and one or more non-cryptographic instructions, wherein the functional unit comprises;

a cryptographic execution pipeline configured to execute the one or more cryptographic instructions with a corresponding cryptographic execution latency;

a non-cryptographic execution pipeline configured to execute the one or more non-cryptographic instructions with a corresponding non-cryptographic execution latency that is longer than the cryptographic execution latency; and

a local bypass network configured to bypass results produced by the cryptographic execution pipeline to dependent cryptographic instructions executing within the cryptographic execution pipeline, such that each instruction within a sequence of dependent cryptographic instructions is executable with an execution latency corresponding to the cryptographic execution latency, and wherein the results of the cryptographic execution pipeline are not bypassed to any other functional unit within the processor.

2. The processor as recited in claim 1, wherein the functional unit is further configured to supply results produced by the cryptographic execution pipeline to dependent non-cryptographic instructions with an execution latency corresponding to the non-cryptographic execution latency, such that an execution latency of a given cryptographic instruction from the perspective of a given dependent instruction depends upon whether the given dependent instruction is a cryptographic instruction or a non-cryptographic instruction.

3. The processor as recited in claim 1, further comprising a bypass network configured to bypass results produced by the functional unit to other ones of a plurality of functional units that includes the functional unit, wherein results produced by the cryptographic execution pipeline are available for bypass to other functional units with an execution latency corresponding to the non-cryptographic execution latency.

4. The processor as recited in claim 1, wherein the one or more cryptographic instructions include an instruction that is executable within the cryptographic execution pipeline to perform one or more rounds of a block cipher.

5. The processor as recited in claim 1, wherein the one or more cryptographic instructions include a chaining instruction that is executable within the cryptographic execution pipeline to perform a chaining operation with respect to blocks of a block cipher.

6. The processor as recited in claim 5, wherein the functional unit is configured to perform floating-point arithmetic and wherein the chaining instruction is a floating-point logical XOR instruction.

7. The processor as recited in claim 6, wherein the cryptographic execution pipeline is configured to execute all floating-point logical instructions defined within the ISA, and wherein all floating-point arithmetic instructions defined within the ISA are executable by the non-cryptographic execution pipeline or another pipeline distinct from the cryptographic execution pipeline.

8. A method, comprising:

a hardware processor issuing instructions for execution, wherein the instructions are programmer-selectable from a defined instruction set architecture (ISA);

a hardware functional unit of the processor receiving instructions for execution, wherein the instructions include one or more cryptographic instructions and one or more non-cryptographic instructions;

the functional unit executing the one or more cryptographic instructions in a cryptographic execution pipeline with a corresponding cryptographic execution latency;

the functional unit executing the one or more non-cryptographic instructions in a non-cryptographic execution pipeline with a corresponding non-cryptographic execution latency that is longer than the cryptographic execution latency; and

the functional unit bypassing results produced by the cryptographic execution pipeline to dependent cryptographic instructions executing within the cryptographic execution pipeline, such that each instruction within a sequence of dependent cryptographic instructions executes with an execution latency corresponding to the cryptographic execution latency, and wherein the results of the cryptographic execution pipeline are not bypassed to any other functional unit within the processor.

9. The method as recited in claim 8, further comprising:

the functional unit supplying results produced by the cryptographic execution pipeline to dependent non-cryptographic instructions with an execution latency corresponding to the non-cryptographic execution latency, such that an execution latency of a given cryptographic instruction from the perspective of a given dependent instruction depends upon whether the given dependent instruction is a cryptographic instruction or a non-cryptographic instruction.

10. The method as recited in claim 8, further comprising:

a bypass network bypassing results produced by the functional unit to other ones of a plurality of functional units that includes the functional unit, wherein results produced by the cryptographic execution pipeline are bypassed to other functional units with an execution latency corresponding to the non-cryptographic execution latency.

11. The method as recited in claim 8, wherein the one or more cryptographic instructions include an instruction that is executable within the cryptographic execution pipeline to perform one or more rounds of a block cipher.

12. The method as recited in claim 8, wherein the one or more cryptographic instructions include a chaining instruction that is executable within the cryptographic execution pipeline to perform a chaining operation with respect to blocks of a block cipher.

13. The method as recited in claim 12, wherein the functional unit is configured to perform floating-point arithmetic and wherein the chaining instruction is a floating-point logical XOR instruction.

14. The method as recited in claim 13, wherein the cryptographic execution pipeline is configured to execute all floating-point logical instructions defined within the ISA, and wherein all floating-point arithmetic instructions defined within the ISA are executable by the non-cryptographic execution pipeline or another pipeline distinct from the cryptographic execution pipeline.

15. A system, comprising:

a system memory; and

a processor coupled to the system memory, wherein the processor comprises;

a hardware instruction fetch unit configured to issue instructions for execution, wherein the instructions are programmer-selectable from a defined instruction set architecture (ISA); and

a hardware functional unit configured to receive instructions for execution from the instruction fetch unit, wherein the instructions include one or more cryptographic instructions and one or more non-cryptographic instructions, wherein the functional unit comprises;

a cryptographic execution pipeline configured to execute the one or more cryptographic instructions with a corresponding cryptographic execution latency;

a non-cryptographic execution pipeline configured to execute the one or more non-cryptographic instructions with a corresponding non-cryptographic execution latency that is longer than the cryptographic execution latency; and

a local bypass network configured to bypass results produced by the cryptographic execution pipeline to dependent cryptographic instructions executing within the cryptographic execution pipeline, such that each instruction within a sequence of dependent cryptographic instructions is executable with an execution latency corresponding to the cryptographic execution latency, and wherein the results of the cryptographic execution pipeline are not bypassed to any other functional unit within the processor.

16. The system as recited in claim 15, wherein the functional unit is further configured to supply results produced by the cryptographic execution pipeline to dependent non-cryptographic instructions with an execution latency corresponding to the non-cryptographic execution latency, such that an execution latency of a given cryptographic instruction from the perspective of a given dependent instruction depends upon whether the given dependent instruction is a cryptographic instruction or a non-cryptographic instruction.

17. The system as recited in claim 15, further comprising a bypass network configured to bypass results produced by the functional unit to other ones of a plurality of functional units that includes the functional unit, wherein results produced by the cryptographic execution pipeline are available for bypass to other functional units with an execution latency corresponding to the non-cryptographic execution latency.

18. The system as recited in claim 15, wherein the one or more cryptographic instructions include an instruction that is executable within the cryptographic execution pipeline to perform one or more rounds of a block cipher.

19. The system as recited in claim 15, wherein the one or more cryptographic instructions include a chaining instruction that is executable within the cryptographic execution pipeline to perform a chaining operation with respect to blocks of a block cipher.

20. The system as recited in claim 15, wherein the cryptographic execution pipeline is configured to execute all floating-point logical instructions defined within the ISA, and wherein all floating-point arithmetic instructions defined within the ISA are executable by the non-cryptographic execution pipeline or another pipeline distinct from the cryptographic execution pipeline.