SEMICONDUCTOR DEVICE

• US 20110089419A1
• Filed: 10/19/2010
• Published: 04/21/2011
• Est. Priority Date: 10/21/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Watanabe, Kazunori, Harada, Hikaru, Noda, Kosei, Yamazaki, Shunpei, Tsubuku, Masashi, Toyotaka, Kouhei
• Granted Patent: US 8,803,142 B2
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: G06F 15/76 Architectures of general purpose stored program computers with program plugboard G06F15/08; multicomputers G06F15/16
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 28/60 Electrodes
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices
• CPC Class Codes: H10B 10/125 the MOSFET being a thin film transistor [TFT]
• CPC Class Codes: H10B 10/15 comprising a resistor load element
• CPC Class Codes: H10B 12/05 Making the transistor
• CPC Class Codes: H10B 12/30 DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells

Abstract

An object is to provide a memory device including a memory element that can be operated without problems by a thin film transistor with a low off-state current. Provided is a memory device in which a memory element including at least one thin film transistor that includes an oxide semiconductor layer is arranged as a matrix. The thin film transistor including an oxide semiconductor layer has a high field effect mobility and low off-state current, and thus can be operated favorably without problems. In addition, the power consumption can be reduced. Such a memory device is particularly effective in the case where the thin film transistor including an oxide semiconductor layer is provided in a pixel of a display device because the memory device and the pixel can be formed over one substrate.

Claims

1. A semiconductor device comprising:

a first line;

a second line; and

a memory element, the memory element comprising;

a capacitor; and

a transistor, the transistor comprising;

an oxide semiconductor layer wherein at least a channel formation region is formed in the oxide semiconductor layer; and

a gate electrode with a gate insulating film interposed between the channel formation region and the gate electrode,

wherein one of a source and a drain of the transistor is electrically connected to the first line,

wherein the other of the source and the drain of the transistor is electrically connected to one of terminals of the capacitor,

wherein the other of the terminals of the capacitor is electrically connected to the second line,

wherein a carrier concentration in the oxide semiconductor layer is less than or equal to 5×

10¹⁴ cm<sup>−

3</sup>, and

wherein a value of off-state current of the transistor is less than 1×

10<sup>−

13</sup> A.

2. The semiconductor device according to claim 1,

wherein a hydrogen concentration in the oxide semiconductor layer is less than or equal to 5×

10¹⁹ cm<sup>−

3</sup>.

3. The semiconductor device according to claim 1, wherein the memory element is arranged in matrix.

4. The semiconductor device according to claim 1, wherein the semiconductor device is a DRAM.

5. A semiconductor device comprising:

a first line;

a second line; and

a memory element, the memory element comprising;

a capacitor; and

a transistor, the transistor comprising;

an oxide semiconductor layer;

a gate electrode; and

a first insulating layer over the gate electrode,

wherein at least a channel formation region is formed in the oxide semiconductor layer,

wherein the channel formation region is provided over the gate electrode with the first insulating layer interposed therebetween,

wherein one of a source and a drain of the transistor is electrically connected to the first line,

wherein the other of the source and the drain of the transistor is electrically connected to one of terminals of the capacitor,

wherein the other of the terminals of the capacitor is electrically connected to the second line,

wherein a carrier concentration in the oxide semiconductor layer is less than or equal to 5×

10¹⁴ cm<sup>−

3</sup>, and

wherein a value of off-state current of the transistor is less than 1×

10<sup>−

13</sup> A.

6. The semiconductor device according to claim 5,

wherein a hydrogen concentration in the oxide semiconductor layer is less than or equal to 5×

10¹⁹ cm<sup>−

3</sup>.

7. The semiconductor device according to claim 5, further comprising a second insulating layer over the channel formation region.

8. The semiconductor device according to claim 5, wherein the memory element is arranged in matrix.

9. The semiconductor device according to claim 5, wherein the semiconductor device is a DRAM.

10. A semiconductor device comprising:

a memory element, the memory element comprising;

a transistor, the transistor comprising;

an oxide semiconductor layer,

wherein at least a channel formation region is formed in the oxide semiconductor layer,

wherein a carrier concentration in the oxide semiconductor layer is less than or equal to 5×

10¹⁴ cm<sup>−

3</sup>, and

wherein a value of off-state current of the transistor is less than 1×

10<sup>−

13</sup> A.

11. The semiconductor device according to claim 10,

wherein a hydrogen concentration in the oxide semiconductor layer is less than or equal to 5×

10¹⁹ cm<sup>−

3</sup>.

12. The semiconductor device according to claim 10, wherein the memory element is arranged in matrix.

13. The semiconductor device according to claim 10, wherein the semiconductor device is a DRAM.

14. The semiconductor device according to claim 10, wherein the semiconductor device is a SRAM.