Method for Manufacturing a Low Defect Interface Between a Dielectric and a III-V Compound

• US 20110089469A1
• Filed: 10/01/2010
• Published: 04/21/2011
• Est. Priority Date: 10/02/2009
• Status: Active Grant

• Current Assignee: IMEC International
• Original Assignee: IMEC International
• Inventors: Merckling, Clement
• Granted Patent: US 8,314,017 B2
• Time in Patent Office: Days
• US Class Current: 257/201
• CPC Class Codes: H01L 21/28264 the insulator being formed after the semiconductor body, the semiconductor being a III-V compound
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H01L 29/20 including, apart from doping materials or other impurities, only AIIIBV compounds
• CPC Class Codes: H01L 29/51 Insulating materials associated therewith for MIS structures on thin film semiconductor H01L29/4908
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66462 with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT

Abstract

The present invention is related to a method for manufacturing a low defect interface between a dielectric material and an III-V compound. More specifically, the present invention relates to a method for manufacturing a passivated interface between a dielectric material and an III-V compound. The present invention is also directed to a device comprising a low defect interface between a dielectric material and an III-V compound that has improved performance.

Claims

1. A method for manufacturing a passivated interface between a dielectric material and a III-V compound, the method comprising:

(a) providing a substrate comprising an exposed region comprising a first III-V compound; and

thereupon

(b) forming at least one intermediate layer comprising a second III-V compound; and

thereafter

(c) applying a thermal treatment in ultra-high-vacuum to the substrate such that upon reaching a first temperature (T₁) a surface reconstruction of the second III-V compound takes place, thereby forming a group III element-rich surface;

(d) bringing the substrate containing the group III element-rich surface to a second temperature (T₂) and subjecting the group III element-rich surface to an ambient comprising a chalcogenide hydride gas, thereby forming a chalcogenide passivated surface; and

(e) forming a dielectric layer on the chalcogenide passivated surface, thereby forming a passivated interface between the dielectric layer and the second III-V compound.

2. A method according to claim 1, wherein step b) is performed under ultra-high-vacuum, and wherein no vacuum break is applied between the steps (b) and (e).

3. A method according to claim 1, wherein any of the first III-V compound or the second III-V compound is selected from the group consisting of III-V compounds comprising As, and any combinations or mixtures thereof.

4. A method according to claim 1, wherein the first III-V compound and the second III-V compound have the same chemical composition.

5. A method according to claim 1, wherein the first temperature (T₁) is between 400°

C. and 600°

C.

6. A method according to claim 1, wherein the second temperature (T₂) is between 15°

C. and 400°

C.

7. A method according to claim 1, wherein the group III element-rich surface obtained in step c) exhibits a surface reconstruction with a (×

4) symmetry along the [110] azimuth.

8. A method according to claim 1, wherein the chalcogenide passivated surface obtained in step d) exhibits a (2×

1) symmetry.

9. A method according to claim 1, wherein the second III-V compound comprises GaAs, wherein the first temperature (T₁) is between 580°

C. and 600°

C.; and

wherein the second temperature (T₂) is between 350°

C. and 400°

C.

10. A method according to claim 1, wherein the step of subjecting the group III element-rich surface to an ambient comprising a chalcogenide hydride is plasma assisted, and wherein the second temperature (T₂) is room temperature.

11. A method according to claim 1, wherein the chalcogenide hydride gas is selected from the group consisting of H₂S, H₂Se, H₂Te, and any combinations or mixtures thereof.

12. A method according to claim 1, wherein the dielectric layer comprises a high-κ

dielectric.

13. A method according to claim 1, wherein step b) comprises the steps of:

forming a first intermediate layer overlying and in contact with the exposed region;

forming a second intermediate layer overlying and in contact with the first intermediate layer;

forming a third intermediate layer overlying and in contact with the second intermediate layer; and

forming a fourth intermediate layer overlying and in contact with the third intermediate layer;

wherein the first and the third intermediate layer comprise a third III-V compound selected to have a large band gap, and wherein the second and the fourth intermediate layer comprise a second III-V compound selected to have a narrow band gap.

14. A method according to claim 1, which further comprises performing a post-deposition anneal after the step of forming the dielectric layer.

15. A method according to claim 14, wherein the post-deposition anneal is performed in an inert ambient.

18. An electronic device made by the method according to claim 1.

16. An electronic device having a passivated interface between a dielectric material and a III-V compound, wherein the device comprises:

a substrate comprising an exposed region comprising a first III-V compound; and

thereupon

at least one intermediate layer comprising a second III-V compound;

a dielectric layer overlying the at least one intermediate layer comprising a second III-V compound; and

at the interface between the second III-V compound and the dielectric, a chalcogenide passivation layer consisting essentially of chalcogenide atom-Group III atom bonds.

17. A device according to claim 16, wherein the at least one intermediate layer comprises:

a first intermediate layer overlying and in contact with the exposed region;

a second intermediate layer overlying and in contact with the first intermediate layer;

a third intermediate layer overlying and in contact with the second intermediate layer; and

a fourth intermediate layer overlying and in contact with the third intermediate layer;

wherein the first and the third intermediate layer comprise a third III-V compound selected to have a large band gap, and wherein the second and the fourth intermediate layer comprise a second III-V compound selected to have a narrow band gap.