MEMORY DEVICE AND SEMICONDUCTOR DEVICE
First Claim
1. A memory device comprising:
- a transistor comprising a first impurity region, a second impurity region, and a channel forming region between the first impurity region and the second impurity region, wherein each of the first impurity region and the second impurity region has one of an n-type conductivity and a p-type conductivity and includes a first impurity for imparting the one of the n-type conductivity or the p-type conductivity;
a diode comprising an n-type impurity region and a p-type impurity region being in direct contact with the n-type impurity region;
a memory element electrically connected to a first terminal of the diode; and
a wiring electrically connected to a second terminal of the diode;
wherein the n-type impurity region or the p-type impurity region of the diode includes a second impurity for imparting the same conductivity as that of the first impurity, andwherein a concentration of the first impurity included in at least one of the first impurity region and the second impurity region is the same or substantially same as a concentration of the second impurity included in the one of the n-type impurity region and the p-type impurity region of the diode.
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Accused Products
Abstract
A memory device capable of data writing at a time other than during manufacturing is provided by using a memory element including an organic material. In a memory cell, a third conductive film, an organic compound, and a fourth conductive film are stacked over a semiconductor film provided with an n-type impurity region and a p-type impurity region, and a pn-junction diode is serially connected to the memory element. A logic circuit for controlling the memory cell includes a thin film transistor. The memory cell and the logic circuit are manufactured over one substrate at the same time. The n-type impurity region and the p-type impurity region of the memory cell are manufactured at the same time as the impurity region of the thin film transistor.
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Citations
45 Claims
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1. A memory device comprising:
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a transistor comprising a first impurity region, a second impurity region, and a channel forming region between the first impurity region and the second impurity region, wherein each of the first impurity region and the second impurity region has one of an n-type conductivity and a p-type conductivity and includes a first impurity for imparting the one of the n-type conductivity or the p-type conductivity; a diode comprising an n-type impurity region and a p-type impurity region being in direct contact with the n-type impurity region; a memory element electrically connected to a first terminal of the diode; and a wiring electrically connected to a second terminal of the diode; wherein the n-type impurity region or the p-type impurity region of the diode includes a second impurity for imparting the same conductivity as that of the first impurity, and wherein a concentration of the first impurity included in at least one of the first impurity region and the second impurity region is the same or substantially same as a concentration of the second impurity included in the one of the n-type impurity region and the p-type impurity region of the diode. - View Dependent Claims (2, 3, 4, 5, 6, 7, 40)
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8. A memory device comprising:
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a transistor comprising a first impurity region, a second impurity region, and a channel forming region between the first impurity region and the second impurity region; a diode comprising an n-type impurity region and a p-type impurity region being in direct contact with the n-type impurity region; a memory element electrically connected to one of the n-type impurity region and the p-type impurity region; and a wiring electrically connected to the other of the n-type impurity region and the p-type impurity region; wherein the first impurity region and the second impurity region comprise an impurity imparting one conductive type to the first impurity region and the second impurity region, and wherein a concentration of the impurity is different from that of one of the n-type impurity region and the p-type impurity region. - View Dependent Claims (9, 10, 11, 12, 13, 14, 41)
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15. A memory device comprising:
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a thin film transistor comprising a first semiconductor film including a first impurity region, a second impurity region, and a channel forming region between the first impurity region and the second impurity region; a diode comprising a second semiconductor film including an n-type impurity region and a p-type impurity region being in direct contact with the n-type impurity region; a memory element electrically connected to one of the n-type impurity region and the p-type impurity region; and a wiring electrically connected to the other of the n-type impurity region and the p-type impurity region; wherein the first semiconductor film and the second semiconductor film are provided over the same insulating surface. - View Dependent Claims (16, 17, 18, 42)
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19. A semiconductor device comprising:
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a memory portion comprising; a transistor comprising a first impurity region, a second impurity region, and a channel forming region between the first impurity region and the second impurity region, wherein each of the first impurity region and the second impurity region has one of an n-type conductivity and a p-type conductivity and includes a first impurity for imparting the one of the n-type conductivity or the p-type conductivity; a diode comprising an n-type impurity region and a p-type impurity region being in direct contact with the n-type impurity region; a memory element electrically connected to one of the n-type impurity region and the p-type impurity region; a wiring electrically connected to the other of the n-type impurity region and the p-type impurity region; and an antenna functionally connected to the memory portion through a controlling circuit, wherein the n-type impurity region or the p-type impurity region of the diode includes a second impurity for imparting the same conductivity as that of the first impurity, and wherein a concentration of the first impurity comprised in at least one of the first impurity region and the second impurity region is the same or substantially same as a concentration of the second impurity in the one of the n-type impurity region and the p-type impurity region of the diode. - View Dependent Claims (20, 21, 22, 23, 24, 25, 26, 43)
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27. A semiconductor device comprising:
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a memory portion comprising; a transistor comprising a first impurity region, a second impurity region, and a channel forming region between the first impurity region and the second impurity region; a diode comprising an n-type impurity region and a p-type impurity region being in direct contact with the n-type impurity region; a memory element electrically connected to one of the n-type impurity region and the p-type impurity region; a wiring electrically connected to the other of the n-type impurity region and the p-type impurity region; and an antenna functionally connected to the memory portion through a controlling circuit, wherein the first impurity region and the second impurity region comprise an impurity imparting one conductive type to the first impurity region and the second impurity region, and wherein a concentration of the impurity is same or substantially same as that of one of the n-type impurity region and the p-type impurity region. - View Dependent Claims (28, 29, 30, 31, 32, 33, 34, 44)
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35. A semiconductor device comprising:
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a memory portion comprising; a thin film transistor comprising a first semiconductor film including a first impurity region, a second impurity region, and a channel forming region between the first impurity region and the second impurity region; a diode comprising a second semiconductor film including an n-type impurity region and a p-type impurity region being in direct contact with the n-type impurity region; a memory element electrically connected to one of the n-type impurity region and the p-type impurity region; and a wiring electrically connected to the other of the n-type impurity region and the p-type impurity region; and an antenna functionally connected to the memory portion through a controlling circuit, wherein the first semiconductor film and the second semiconductor film are provided over the same insulating surface. - View Dependent Claims (36, 37, 38, 39, 45)
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Specification