SUPER-HIGH DENSITY TRENCH MOSFET

• US 20110089486A1
• Filed: 05/26/2010
• Published: 04/21/2011
• Est. Priority Date: 10/20/2009
• Status: Active Grant

• Current Assignee: Vishay Siliconix
• Original Assignee: Vishay Siliconix
• Inventors: Lichtenberger, Karl, Xu, Robert Q., Shi, Sharon, Terrill, Kyle, Chen, Kuo-In, Chen, Qufei
• Granted Patent: US 9,431,530 B2
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/0638 for preventing surface leakage due to surface inversion layer, e.g. with channel stopper channel stoppers in combination with isolation region for integrated circuits H01L21/762
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A method, in one embodiment, can include forming a plurality of trenches in a body region for a vertical metal-oxide semiconductor field-effect transistor (MOSFET). In addition, the method can include angle implanting source regions into the body region. Furthermore, dielectric material can be grown within the plurality of trenches. Gate polysilicon can be deposited within the plurality of trenches. Moreover, the method can include chemical mechanical polishing the gate polysilicon. The method can also include etching back the gate polysilicon within the plurality of trenches.

Claims

1. A method comprising:

forming a plurality of trenches in a body region for a vertical metal-oxide semiconductor field-effect transistor (MOSFET);

angle implanting source regions into said body region;

growing dielectric material within said plurality of trenches;

depositing gate polysilicon within said plurality of trenches;

chemical mechanical polishing said gate polysilicon; and

etching back said gate polysilicon within said plurality of trenches.

2. The method of claim 1, further comprising:

depositing dielectric material over said etched back gate polysilicon; and

chemical mechanical polishing said dielectric material.

3. The method of claim 2, further comprising:

self-aligning a source contact over said dielectric material and said source regions.

4. The method of claim 3, wherein said source contact is in contact with at least one of said source regions.

5. The method of claim 1, further comprising:

forming an epitaxial region on a substrate.

6. The method of claim 5, wherein said epitaxial region is P−

and said substrate is P++.

7. The method of claim 5, wherein said epitaxial region is N−

and said substrate is N++.

8. A method comprising:

forming an edge termination trench in an epitaxial region of a device;

depositing dielectric material within said edge termination trench;

depositing polysilicon within said edge termination trench;

chemical mechanical polishing said polysilicon; and

etching back said polysilicon within said edge termination trench.

9. The method of claim 8, further comprising:

depositing dielectric material over said etched back polysilicon; and

chemical mechanical polishing said dielectric material.

10. The method of claim 9, further comprising:

depositing a low temperature oxide (LTO) and borophosphosilicate glass (BPSG) above said dielectric material.

11. The method of claim 8, further comprising:

forming a body region within said epitaxial region, wherein said edge termination trench surrounds said body region.

12. The method of claim 8, wherein said forming further comprises forming a plurality of gate trenches in a body region for a vertical metal-oxide semiconductor field-effect transistor (MOSFET).

13. The method of claim 12, wherein said depositing polysilicon further comprises depositing polysilicon within said gate trench.

14. The method of claim 13, wherein said chemical mechanical polishing further comprising chemical mechanical polishing said polysilicon within said gate trench.

15. The method of claim 14, wherein said etching back further comprising etching back said polysilicon within said gate trench.

16. A device comprising:

a plurality of trenches within a body region for a vertical metal-oxide semiconductor field-effect transistor (MOSFET), wherein said plurality of trenches each comprises a gate polysilicon encompassed by a dielectric material, wherein the upper surface of said dielectric material is planarized;

a source contact; and

a plurality of mesas that define said plurality of trenches, each of said plurality of mesas comprises a source region contacting said source contact.

17. The device of claim 16, wherein said plurality of trenches has a density of at least 1 giga-cells within 20 square millimeters.

18. The device of claim 16, wherein each of said plurality of trenches has a cell pitch of 0.8 micrometers or lower and a depth of approximately 1 micrometer.

19. The device of claim 16, further comprising:

a edge termination trench within said body region, wherein said termination trench comprises a termination polysilicon encompassed by a dielectric material, wherein the upper surface of said dielectric material is planarized.

20. The device of claim 16, wherein said edge termination trench is wider than a gate contact of said vertical MOSFET.