Magnetic Random Access Memory (MRAM) Manufacturing Process for a Small Magnetic Tunnel Junction (MTJ) Design with a Low Programming Current Requirement

• US 20110089511A1
• Filed: 12/21/2010
• Published: 04/21/2011
• Est. Priority Date: 02/12/2007
• Status: Active Grant

• Current Assignee: Avalanche Technology Incorporated
• Original Assignee: Avalanche Technology Incorporated
• Inventors: MALMHALL, Roger Klas, KESHTBOD, Parviz, RANJAN, Rajiv Yadav
• Granted Patent: US 8,542,524 B2
• Time in Patent Office: Days
• US Class Current: 257/422
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: G11C 11/161 details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
• CPC Class Codes: H10B 61/22 of the field-effect transistor [FET] type
• CPC Class Codes: H10N 50/01 Manufacture or treatment
• CPC Class Codes: H10N 50/10 Magnetoresistive devices

Abstract

A method of making a magnetic random access memory cell includes forming a magnetic tunnel junction (MTJ) on top of a wafer, depositing oxide on top of the MTJ, depositing a photo-resist layer on top of the oxide layer, forming a trench in the photo-resist layer and oxide layer where the trench has a width that is substantially the same as that of the MTJ. Then, the photo-resist layer is removed and a hard mask layer is deposited on top of the oxide layer in the trench and the wafer is planarized to remove the portion of the hard mask layer that is not in the trench to substantially level the top of oxide layer and the hard layer on the wafer. The remaining oxide layer is etched and the the MTJ is etched to remove the portion of the MTJ which is not covered by the hard mask layer.

Claims

1. A method of making a magnetic random access memory cell comprising:

a. forming a magnetic tunnel junction (MTJ) on top of a wafer;

b. depositing oxide on top of the MTJ;

c. depositing a photo-resist layer on top of the oxide layer;

d. forming a trench in the photo-resist layer and oxide layer, the trench having a width that is substantially the same as that of the MTJ;

e. removing the photo-resist layer;

f. depositing a hard mask layer on top of the oxide layer in the trench;

g. planarizing the wafer to remove the portion of the hard mask layer that is not in the trench, and to substantially level the top of oxide layer and the hard layer on the wafer; and

h. etching the remaining oxide layer; and

i. etching the MTJ to remove the portion of the MTJ which is not covered by the hard mask layer.

2. A method of making a magnetic random access memory cell, as recited in claim 1, wherein step d. comprises:

forming a partial trench in the photo-resist layer that is substantially the same size as the width of the MTJ;

etching through the oxide layer to form a trench, wherein the oxide layer is removed above the MTJ; and

removing the remaining photo-resist layer from the wafer.

3. A method of making a magnetic random access memory cell, as recited in claim 1, further comprising:

j. depositing a shielding layer to cover hard mask layer, the exposed conductive layer, and the exposed wafer;

k. planarizing the second nitride layer, such that it is substantially flat

l. depositing a second oxide layer to substantially cover the shielding layer;

m. depositing a second shielding layer to substantially cover the second oxide layer;

n. depositing a third oxide layer to substantially cover the second shielding layer;

o. depositing a second photo-resist layer to substantially cover the third oxide layer;

p. forming two oxide trenches in the second oxide layer, wherein each oxide trench is substantially centered over the conductive layer;

q. depositing a third photo-resist layer to substantially fill both trenches and to cover the remaining second oxide layer and the exposed second shielding layer;

r. forming a via trench through the second oxide layer, second shielding layer, and first oxide layer, wherein the via trench is centered over the conductive layer without the MTJ, and further wherein the top of the conductive layer forms the bottom of via trench;

s. removing the third photo-resist layer;

t. depositing a fourth photo-resist layer to substantially fill the via trench and cover the remaining second oxide layer and exposed second shielding layer;

u. forming a MTJ trench through the second oxide layer, second shielding layer, first oxide layer, and first shielding layer, wherein the top of the hard mask layer, the remaining first shielding layer, and the remaining oxide layer form the bottom of the MTJ trench;

v. removing the fourth photo-resist layer; and

w. depositing a second conductive layer to fill both the MTJ trench and the via trench.

4. A method of making a magnetic random access memory cell, as recited claim 1, wherein during the planarization step g., chemical-mechanical polishing (CMP) is used to remove the portion of the hard mask that is not in the trench.

5. A method of making a magnetic random access memory cell, as recited in claim 1, wherein the MTJ has an aspect ratio, defined by the ratio of length of the MTJ to the width thereof, of 1.3-1.5.

6. A method of making a magnetic random access memory cell, as recited in claim 1, wherein the oxide deposited is silicon dioxide (SiO₂).

7. A method of making a magnetic random access memory cell, as recited in claim 1, wherein step f. uses a Damascene Process to deposit the hard mask layer.

8. A method of making a magnetic random access memory cell, as recited in claim 1, wherein the MTJ is approximately 300 Angstroms high.

9. A method of making a magnetic random access memory cell, as recited in claim 1, wherein the photo-resist layer is removed by plasma ashing.

10. A method of making a magnetic random access memory cell, as recited in claim 1, wherein the deposition of the oxide layer in step b. is performed using chemical vapor deposition (CVD).

11. A method of making a magnetic random access memory cell, as recited in claim 1, wherein the deposition of the oxide layer in step b. is performed using oxide sputtering.

12. A method of making a magnetic random access memory cell, as recited in claim 1, wherein in step d. the trench is formed by etching with tetra-fluoro-Carbon (CF₄).

13. A method of making a magnetic random access memory cell, as recited in claim 1, wherein the hard mask layer deposited inside the trench at step f. is approximately 650 Angstroms wide and 1500 Angstroms tall.

14. A method of making a magnetic random access memory cell, as recited in claim 1, wherein during the forming a magnetic tunnel junction (MTJ) on top of the wafer, a minimum amount of copper and a minimum amount of titanium (Ti) is applied atop the MTJ.

15. A method of making a magnetic random access memory cell, as recited in claim 1, wherein during the forming a magnetic tunnel junction (MTJ) on top of a wafer, a minimum amount of copper and a minimum amount of ruthenium (Ru) is applied atop the MTJ.

16. A method of making a magnetic random access memory cell, as recited in claim 1, wherein the hard mask layer is made of a material from a group consisting of:

tungsten (W), titanium (Ti), titanium nitride (TiN), and tantalum (TaNi).

17. A magnetic random access memory cell, comprising:

a complimentary metal-oxide-semiconductor (CMOS) wafer;

a conductive layer formed on top of the CMOS wafer;

a magnetic tunnel junction (MTJ) centered on top of the conductive layer;

a hard mask layer, formed on top of the MTJ; and

a shielding layer, wherein the shielding layer covers the hard mask layer, the sides of the MTJ, and the exposed portion of the conductive layer

18. A magnetic random access memory cell, as recited in claim 17, further comprising:

a oxide layer, formed on top of the shielding layer;

a second shielding layer, formed on top of the oxide layer;

a second oxide layer, formed on top of the second shielding layer;

a second conductive layer; and

a MTJ trench, wherein the trench is filled with the second conductive layer, and the trench spans from the top of the second oxide layer down through the second oxide layer, second shielding layer, oxide layer, and first shielding layer such that the top of the hard mask layer forms the bottom of MTJ trench.

19. A magnetic random access memory cell, as recited in claim 17, further comprising:

a via trench, wherein the trench is filled with the second conductive layer, and the trench spans from the top of the second oxide layer down through the second oxide layer, second shielding layer, oxide layer, and first shielding layer such that the conductive layer forms the bottom of the via trench.