SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING

• US 20110089527A1
• Filed: 12/22/2010
• Published: 04/21/2011
• Est. Priority Date: 01/16/2009
• Status: Active Grant

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: Blank, Oliver
• Granted Patent: US 8,188,567 B2
• Time in Patent Office: Days
• US Class Current: 257/520
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor and method for manufacturing a semiconductor device. In one embodiment the method includes providing a semiconductor substrate with a first substrate surface and at least one trench having at least one trench surface. The trench extends from the first substrate surface into the semiconductor substrate. The trench has a first trench section and a second trench section. The trench surface is exposed in an upper portion of the first and second trench sections and covered with a first insulating layer in a lower portion. A second insulating layer is formed at least on the exposed trench surface in the upper portion. A conductive layer is formed on the second insulating layer at least in the upper portion, wherein the second insulating layer electrically insulates the conductive layer from the semiconductor substrate. The conductive layer is removed in the first trench section without removing the conductive layer in the second trench section.

Claims

1. A semiconductor device, comprising:

a semiconductor substrate comprising a first substrate surface and at least one trench comprising at least one trench surface, the trench extending from the first substrate surface into the semiconductor substrate, in a longitudinal direction and comprising a first trench section and a second trench section which is arranged adjacent, in the longitudinal direction, to the first trench section;

a first insulating layer covering the trench surface in a lower portion of the first and second trench sections;

a second insulating layer covering the trench surface in an upper portion of the first and second trench sections, the second insulating layer being thinner than the first insulating layer;

a conductor region on the second insulating layer in the second trench section, the conductor region extending from an upper surface or edge of the first insulating layer at least to the first substrate surface; and

a third insulating layer on the second insulating layer in the first trench section, the third insulating layer extending from an upper surface or edge of the first insulating layer at least to the first substrate surface.

2. The semiconductor device of claim 1, comprising wherein the first insulating layer is a thermal oxide layer.

3. The semiconductor device of claim 1, comprising wherein the second insulating layer is a thermal oxide layer.

4. The semiconductor device of claim 1, comprising wherein the third insulating layer is a deposition oxide layer.

5. The semiconductor device of claim 1, wherein the second insulating layer comprises a constant thickness in the longitudinal direction at least at the transition between the first and second trench sections.

6. The semiconductor device of claim 1, further comprising:

a field plate region in the first and second trench sections, the field plate region extending from the upper portion into the lower portion and being adjacent to the first insulating layer; and

a fourth insulating layer being arranged in the upper portion of the first trench section between the third insulating layer and the field plate region and in the upper portion of second trench section between the conductor region and the field plate region.

7. The semiconductor device of claim 6, wherein the fourth insulating layer comprises a constant thickness in the longitudinal direction at least at the transition between the first and second trench section.

8. The semiconductor device of claim 6, comprising wherein the fourth insulating layer is a thermal oxide layer.

9. A semiconductor device, comprising:

a semiconductor substrate comprising a first substrate surface and at least one trench comprising at least one trench surface, the trench extending from the first substrate surface into the semiconductor substrate, in a longitudinal direction and comprising a first trench section and a second trench section which is arranged adjacent, in the longitudinal direction, to the first trench section;

a first insulating layer covering the trench surface in a lower portion of the first and second trench section, the first insulating layer being a thermal oxide layer;

a second insulating layer covering the trench surface in an upper portion of the first and second trench section, the second insulating layer being a thermal oxide layer thinner than the first insulating layer;

a conductor region on the second insulating layer in the second trench section, the conductor region extending from an upper end of the first insulating layer at least to the first substrate surface; and

a third insulating layer on the second insulating layer in the first trench section, the third insulating layer extending from an upper end of the first insulating layer at least to the first substrate surface, the third insulating layer being a deposition oxide layer.