Interposer Based Monolithic Microwave Integrate Circuit (iMMIC)

• US 20110089531A1
• Filed: 10/01/2010
• Published: 04/21/2011
• Est. Priority Date: 10/16/2009
• Status: Abandoned Application

• Current Assignee: Teledyne Scientific & Imaging, LLC (Teledyne Technologies Incorporated)
• Original Assignee: Teledyne Scientific & Imaging, LLC (Teledyne Technologies Incorporated)
• Inventors: Tran, Lan, Ha, Wonill, Hacker, Jonathan B., Newell, Scott, Hillman, Christopher E.
• Application Number:
  US12/896,786
• Publication Number:
  US 20110089531A1
• Time in Patent Office: Days
• US Class Current: 257/532
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/24227 the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
• CPC Class Codes: H01L 2224/83 using a layer connector
• CPC Class Codes: H01L 2224/92 Specific sequence of method steps
• CPC Class Codes: H01L 2224/92244 the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/24 of an individual high density interconnect connector
• CPC Class Codes: H01L 24/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/01023 Vanadium [V]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: H01L 2924/10329 Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/13064 High Electron Mobility Transistor [HEMT, HFET [heterostructure FET], MODFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/15165 : Monolayer substrate
• CPC Class Codes: H01L 2924/3011 : Impedance

Abstract

A system is disclosed for IC fabrication, including seating an integrated circuit (“IC”) having at least one contact into a recess of a silicon interposer substrate, applying an insulator in liquid form to fill portions of the recess not otherwise occupied by the IC and to cover a top surface of the IC and the silicon interposer substrate, introducing the insulator to a ramped environmental temperature, holding the environmental temperature at a reflow temperature to reflow the insulator and ramping down the environmental temperature to cure the insulator.

Claims

1. A method of IC fabrication, comprising:

seating an integrated circuit (“

IC”

) having at least one contact into a recess of a silicon interposer substrate;

applying an insulator in liquid form to fill portions of the recess not otherwise occupied by the IC and to cover a top surface of the IC and the silicon interposer substrate;

introducing the insulator to a ramped environmental temperature;

holding the environmental temperature at a reflow temperature to reflow the insulator;

ramping down the environmental temperature to cure the insulator.

2. The method of claim 1, further comprising:

introducing the insulator to a gas extraction temperature, holding at such gas extraction temperature for a gas extraction period to allow formed gas to migrate out of the recess, and then cooling the insulator to approximately room temperature, each prior to the introducing the insulator in liquid form to the ramped environmental temperature step.

3. The method of claim 1, further comprising:

lapping the insulator to a thickness of approximately 2 to 30 microns.

4. The method of claim 3, further comprising:

applying an insulator in liquid form after said lapping step to a layer thickness of approximately 2-4 microns to fill irregularities in a lapped surface of said insulator; and

etching said insulator after said lapping and said applying an insulator steps back approximately 2-4 microns.

5. The method of claim 1, further comprising:

opening a plurality of a vias in the insulator to expose at least one of the at least one contact.

6. The method of claim 5, further comprising:

depositing patterned metal onto the insulator to form conductive portions.

7. A method of IC fabrication, comprising:

seating an integrated circuit (“

IC”

) having at least one contact into a recess of a substrate, the recess having side walls to establish a channel between the substrate and the seated IC;

applying a benzocyclobutene (BCB) layer to portions of said recess not otherwise occupied by the IC and to cover a top surface of the IC and the substrate;

introducing the BCB layer to a ramped environmental temperature of approximately 10°

C. per hour to approximately 150-180°

C.;

holding the BCB layer at approximately 150-180°

C. for approximately 72-100 hours to reflow the BCB for reduction of gaseous voids in the channel;

reducing the environmental temperature of the BCB layer by approximately 10°

C. per hour to approximately room temperature to cure the BCB.

11. The method of claim 7, further comprising:

opening a plurality of a vias in the BCB layer to expose at least one of the at least one contact.

12. The method of claim 11, further comprising:

depositing a patterned metal layer onto the BCB layer to form conductive portions.

13. The method of claim 12, further comprising:

depositing capacitor dielectric material; and

depositing metal on the capacitor dielectric material to form a capacitor.

14. The method according to claim 7, wherein the seating an IC having at least one contact into a recess of a substrate comprises seating the IC into a silicon interposer substrate.

8. The method of 7, further comprising:

introducing the BCB layer to approximately 80°

C. heat, holding at such temperature for approximately 3 minutes, and then cooling the BCB layer to approximately room temperature, each prior to the introducing the BCB to the ramped environmental temperature step.

9. The method of claim 8, further comprising:

repeating the introducing the BCB layer to approximately 80°

C. heat step a plurality of times before the introducing the BCB layer to the ramped environmental temperature step.

10. The method of claim 8, further comprising:

lapping the BCB layer to a thickness of approximately 2 to 30 microns.

15. An apparatus, comprising:

a substrate having a recess;

an integrated circuit (“

IC”

) seated in the recess, the IC having a plurality of contacts;

a benzocyclobutene (“

BCB”

) layer filling portions of the recess not otherwise occupied by the IC and extending onto a face of the substrate;

at least one via extending through the BCB layer to communicate with the contact; and

a patterned metal layer in communication with the contact through the BCB layer;

wherein the patterned metal layer is a first metal interconnect layer that is in communication with the IC through the BCB layer.

16. The apparatus of claim 15, further comprising:

a thin film resistor (TFR) on said substrate; and

at least one TFR via extending through the BCB layer to communication with the TFR through a TFR contact, said TFR via in communication with at least one of said plurality of contacts on the IC through the first metal interconnect layer.

17. The apparatus of claim 15, further comprising:

a capacitor dielectric layer formed on a capacitor plate portion of the patterned metal layer; and

a depositing metal plate on the capacitor dielectric layer;

wherein the capacitor dielectric layer between the depositing metal plate and the capacitor plate portion of the patterned metal layer form a capacitor.

18. The apparatus of claim 17, further comprising:

a second BCB layer formed on said patterned metal layer;

a second patterned metal layer formed on said second BCB layer; and

at least one capacitor via extending through the second BCB layer to communication with the capacitor plate portion of the patterned metal layer, said capacitor via in communication with at least one of said plurality of contacts on the IC through the first metal interconnect layer.

wherein the portion of the patterned metal layer

wherein said the portion of the patterned metal layer is in communication with the contact through vias.

19. An apparatus, comprising:

an integrated circuit (IC) seated in a recess of a silicon interposer substrate, the IC having at least one contact;

a dielectric insulator layer encapsulating at least three sides of the IC and a top surface of the silicon interposer substrate;

a metal via extending through the dielectric insulator layer and contacting at least one of the at least one contact; and

a capacitor on the dielectric insulator layer and in communication with the at least one of the plurality of contacts through a patterned metal layer on the dielectric insulator layer.

20. The apparatus of claim 19, wherein the dielectric insulator layer comprises benzocyclobutene (“

BCB”

).

21. The apparatus of claim 19, further comprising:

a die attach material between said IC and said recess to couple said IC to said recess.