LOGIC CIRCUIT AND SEMICONDUCTOR DEVICE

• US 20110089975A1
• Filed: 10/08/2010
• Published: 04/21/2011
• Est. Priority Date: 10/16/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: YAMAZAKI, Shunpei, KOYAMA, Jun, NODA, Kosei, TSUBUKU, Masashi
• Granted Patent: US 8,400,187 B2
• Time in Patent Office: Days
• US Class Current: 326/102
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A logic circuit includes a thin film transistor having a channel formation region formed using an oxide semiconductor, and a capacitor having terminals one of which is brought into a floating state by turning off the thin film transistor. The oxide semiconductor has a hydrogen concentration of 5×10¹⁹ (atoms/cm³) or less and thus substantially serves as an insulator in a state where an electric field is not generated. Therefore, off-state current of a thin film transistor can be reduced, leading to suppressing the leakage of electric charge stored in a capacitor, through the thin film transistor. Accordingly, a malfunction of the logic circuit can be prevented. Further, the excessive amount of current which flows in the logic circuit can be reduced through the reduction of off-state current of the thin film transistor, resulting in low power consumption of the logic circuit.

Claims

1. A logic circuit comprising:

a thin film transistor having a first terminal and a second terminal,

wherein one of the first terminal and the second terminal is electrically connected to a node which is brought into a floating state by turning off the thin film transistor, and

wherein a channel formation region of the thin film transistor is formed using an oxide semiconductor with a hydrogen concentration of 5×

10¹⁹ atoms/cm³ or less.

2. The logic circuit according to claim 1, further comprising a capacitor,

wherein one terminal of the capacitor is electrically connected to the node.

3. The logic circuit according to claim 1,

wherein the oxide semiconductor is formed using an In—

Ga—

Zn—

O-based oxide semiconductor layer.

4. A semiconductor device comprising the logic circuit according to claim 1.

5. A logic circuit comprising:

a first thin film transistor having a first terminal which is electrically connected to a high power supply potential line;

a second thin film transistor having a gate terminal which is electrically connected to an input terminal, and a first terminal which is electrically connected to a gate terminal and a second terminal of the first thin film transistor;

a third thin film transistor having a gate terminal which is electrically connected to a pulse signal line, a first terminal which is electrically connected to a second terminal of the second thin film transistor, and a second terminal which is electrically connected to a low power supply potential line; and

a fourth thin film transistor having a gate terminal which is electrically connected to the pulse signal line, a first terminal which is electrically connected to the gate terminal and the second terminal of the first thin film transistor and the first terminal of the second thin film transistor, and a second terminal which is electrically connected to an output terminal,

wherein the second terminal of the fourth thin film transistor is electrically connected to a node which is brought into a floating state by turning off the fourth thin film transistor, and

wherein a channel formation region of the fourth thin film transistor is formed using an oxide semiconductor with a hydrogen concentration of 5×

10¹⁹ atoms/cm³ or less.

6. The logic circuit according to claim 5,

wherein channel formation regions of the first to third thin film transistors are each formed using an oxide semiconductor with a hydrogen concentration of 5×

10¹⁹ atoms/cm³ or less.

7. The logic circuit according to claim 5, further comprising a capacitor,

wherein one terminal of the capacitor is electrically connected to the second terminal of the fourth thin film transistor and the output terminal, and

wherein the other terminal of the capacitor is electrically connected to the low power supply potential line.

8. The logic circuit according to claim 5,

wherein the oxide semiconductor is formed using an In—

Ga—

Zn—

O-based oxide semiconductor layer.

9. A semiconductor device comprising the logic circuit according to claim 5.

10. A logic circuit comprising:

a first thin film transistor having a first terminal which is electrically connected to a high power supply potential line;

a second thin film transistor having a gate terminal which is electrically connected to a pulse signal line, and a first terminal which is electrically connected to a gate terminal and a second terminal of the first thin film transistor;

a third thin film transistor having a gate terminal which is electrically connected to an input terminal, a first terminal which is electrically connected to a second terminal of the second thin film transistor, and a second terminal which is electrically connected to a low power supply potential line; and

a fourth thin film transistor having a gate terminal which is electrically connected to the pulse signal line, a first terminal which is electrically connected to the second terminal of the second thin film transistor and the first terminal of the third thin film transistor, and a second terminal which is electrically connected to an output terminal,

wherein the second terminal of the fourth thin film transistor is electrically connected to a node which is brought into a floating state by turning off the fourth thin film transistor, and

wherein a channel formation region of the fourth thin film transistor is formed using an oxide semiconductor having a hydrogen concentration of 5×

10¹⁹ atoms/cm³ or less.

11. The logic circuit according to claim 10,

wherein channel formation regions of the first to third thin film transistors are each formed using an oxide semiconductor with a hydrogen concentration of 5×

10¹⁹ atoms/cm³ or less.

12. The logic circuit according to claim 10, further comprising a capacitor,

wherein one terminal of the capacitor is electrically connected to the second terminal of the fourth thin film transistor and the output terminal, and

wherein the other terminal of the capacitor is electrically connected to the low power supply potential line.

13. The logic circuit according to claim 10,

wherein the oxide semiconductor is formed using an In—

Ga—

Zn—

O-based oxide semiconductor layer.

14. A semiconductor device comprising the logic circuit according to claim 10.

15. A logic circuit comprising:

a first thin film transistor having a gate terminal and a first terminal which are electrically connected to a high power supply potential line;

a second thin film transistor having a gate terminal which is electrically connected to an input terminal, and a first terminal which is electrically connected to a second terminal of the first thin film transistor;

a third thin film transistor having a gate terminal which is electrically connected to a pulse signal line, a first terminal which is electrically connected to a second terminal of the second thin film transistor, and a second terminal which is electrically connected to a low power supply potential line; and

a fourth thin film transistor having a gate terminal which is electrically connected to the pulse signal line, a first terminal which is electrically connected to the second terminal of the first thin film transistor and the first terminal of the second thin film transistor, and a second terminal which is electrically connected to an output terminal,

wherein the second terminal of the fourth thin film transistor is electrically connected to a node which is brought into a floating state by turning off the fourth thin film transistor, and

wherein a channel formation region of the fourth thin film transistor is formed using an oxide semiconductor having a hydrogen concentration of 5×

10¹⁹ atoms/cm³ or less.

16. The logic circuit according to claim 15,

wherein channel formation regions of the first to third thin film transistors are each formed using an oxide semiconductor with a hydrogen concentration of 5×

10¹⁹ atoms/cm³ or less.

17. The logic circuit according to claim 15, further comprising a capacitor,

wherein one terminal of the capacitor is electrically connected to the second terminal of the fourth thin film transistor and the output terminal, and

wherein the other terminal of the capacitor is electrically connected to the low power supply potential line.

18. The logic circuit according to claim 15,

wherein the oxide semiconductor is formed using an In—

Ga—

Zn—

O-based oxide semiconductor layer.

19. A semiconductor device comprising the logic circuit according to claim 15.

20. A logic circuit comprising:

a first thin film transistor having a gate terminal and a first terminal which are electrically connected to a high power supply potential line;

a second thin film transistor having a gate terminal which is electrically connected to a pulse signal line, and a first terminal which is electrically connected to a second terminal of the first thin film transistor;

a third thin film transistor having a gate terminal which is electrically connected to an input terminal, a first terminal which is electrically connected to a second terminal of the second thin film transistor, and a second terminal which is electrically connected to a low power supply potential line; and

a fourth thin film transistor having a gate terminal which is electrically connected to the pulse signal line, a first terminal which is electrically connected to the second terminal of the first thin film transistor and the first terminal of the third thin film transistor, and a second terminal which is electrically connected to an output terminal,

wherein the second terminal of the fourth thin film transistor is electrically connected to a node which is brought into a floating state by turning off the fourth thin film transistor, and

wherein a channel formation region of the fourth thin film transistor is formed using an oxide semiconductor having a hydrogen concentration of 5×

10¹⁹ atoms/cm³ or less.

21. The logic circuit according to claim 20,

wherein channel formation regions of the first to third thin film transistors are each formed using an oxide semiconductor with a hydrogen concentration of 5×

10¹⁹ atoms/cm³ or less.

22. The logic circuit according to claim 20, further comprising a capacitor,

wherein one terminal of the capacitor is electrically connected to the second terminal of the fourth thin film transistor and the output terminal, and

wherein the other terminal of the capacitor is electrically connected to the low power supply potential line.

23. The logic circuit according to claim 20,

wherein the oxide semiconductor is formed using an In—

Ga—

Zn—

O-based oxide semiconductor layer.

24. A semiconductor device comprising the logic circuit according to claim 20.