PROTECTIVE CIRCUIT BOARD COVER

• US 20110090658A1
• Filed: 10/14/2010
• Published: 04/21/2011
• Est. Priority Date: 10/14/2009
• Status: Active Grant

• Current Assignee: Lockheed Martin Corporation (Martin Marietta Corporation)
• Original Assignee: Lockheed Martin Corporation (Martin Marietta Corporation)
• Inventors: Adams, Christian, Nelson, Patrick, Kelley, Matthew
• Granted Patent: US 8,659,908 B2
• Time in Patent Office: Days
• US Class Current: 361/765
• CPC Class Codes: G06F 21/73 by creating or determining hardware identification, e.g. serial numbers
• CPC Class Codes: H01L 23/57 Protection from inspection, reverse engineering or tampering
• CPC Class Codes: H01L 23/573 using passive means
• CPC Class Codes: H01L 23/576 using active circuits
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H05K 1/0275 Security details, e.g. tampering prevention or detection
• CPC Class Codes: H05K 3/284 for encapsulating mounted components H05K1/185 takes precedence
• CPC Class Codes: Y10T 29/49227 Insulator making

Abstract

A protective, anti-tamper coating and methods of coating creation and application are provided. The coating may include an elastomeric layer to allow for strippability/removal. The coating may also include a “smart layer” for tamper detection, imaging prevention, and tamper prevention or underlying device de-activation/alteration upon tamper detection. The coating may also include one or more ground planes around the smart layer and one or more frangible layers designed to interrupt or alter smart layer function in the event of a tamper attempt.

Claims

1. An anti-tamper coating for a component, the coating comprising:

a foundation layer that includes thermal and component connection vias;

a smart layer disposed on top of the foundation layer, the smart layer including at least one active circuit component or signal pathway operably connected to the underlying component through a connection via;

a capping layer disposed on top of the smart layer and configured with a frangible portion such that a tamper attempt breaks the frangible portion, thereby causing physical damage to underlying smart layer components or signal pathways.

2. The coating of claim 1, where the foundation layer includes an elastomeric undercoat and where the undercoat also includes thermal and/or component connection vias.

3. The coating of claim 1, where the smart layer includes at least two sub-layers, each sub-layer including at least one active circuit component or signal pathway operably connected to at least one of an active circuit component or signal pathway in the other sub-layer.

4. The coating of claim 1, where the foundation layer includes a frangible portion such that breakage of the frangible portion causes disruptive or destructive interactions between a smart layer component or signal pathway and the underlying electric component.

5. The coating of claim 1, further including a ground plane layer disposed between the foundation layer and the smart layer.

6. The coating of claim 1, wherein the capping layer includes an electromagnetic shielding portion.

7. The coating of claim 1, further including a ground plane disposed between the smart layer and the capping layer.

8. The coating of claim 1, where the at least one active component includes at least one of a logic device and a memory device.

9. The coating of claim 1, the coating further comprising a first ground plane disposed between the smart layer and the foundation layer and a second ground plane disposed on top of the smart layer.

10. The coating of claim 9, the coating further comprising a second smart layer disposed between the second ground plane and the capping layer

11. The coating of claim 1, where the capping layer includes damage-causing elements contained in the frangible portion such that breaking the frangible portion makes the damage-causing elements physically interact with the smart layer.

12. A method of applying an anti-tamper coating to a component, the method comprising:

first depositing a foundation layer such that first depositing creates or preserves thermal and component connection vias;

second depositing a smart layer on top of the foundation layer, the smart layer including at least one active circuit component or signal pathway operably connected to the underlying component;

third depositing a frangible capping layer on top of the smart layer, where third depositing includes depositing the capping layer in a manner such that a breach of the capping layer causes physical damage to underlying smart layer components or signal pathways.

13. The method of claim 12, the method further comprising depositing an elastomeric undercoat between the foundation layer and the underlying component such that depositing an elastomeric undercoat creates or preserves thermal and/or component connection vias.

14. The method of claim 12, said second depositing further including depositing at least a second smart layer on top of the smart layer, the second smart layer including at least one active component or signal pathway operably connected to at least one of the active circuit component or signal pathway in the smart layer and the underlying component.

15. The method of claim 12, further including depositing a ground plane layer between the foundation layer and the smart layer.

16. The method of claim 12, wherein the capping layer is an electromagnetic shielding layer.

17. The method of claim 12, further including depositing a ground plane between the smart layer and the capping layer.

18. The method of claim 12, where the smart layer includes at least one of a memory component or a logic component and where the method further comprises loading said memory component or said logic component with predetermined operating parameters.

19. The method of claim 18, the method further comprising propagating data based on said predetermined operating parameters to other components in said smart layer.

20. The method of claim 18, where propagating includes burning out or erasing said logic or memory component such that said predetermined operating parameters cannot be recovered.