Magnetic Tunnel Junction Cell Adapted to Store Multiple Digital Values

• US 20110090732A1
• Filed: 12/21/2010
• Published: 04/21/2011
• Est. Priority Date: 03/25/2008
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Zhu, Xiaochun, Kang, Seung H., Li, Xia
• Granted Patent: US 7,995,383 B2
• Time in Patent Office: Days
• US Class Current: 365/158
• CPC Class Codes: G11C 11/161 details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
• CPC Class Codes: G11C 11/1659 Cell access
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods
• CPC Class Codes: G11C 11/5607 using magnetic storage elements
• CPC Class Codes: G11C 19/0808 using magnetic domain propagation
• CPC Class Codes: H10B 61/22 of the field-effect transistor [FET] type
• CPC Class Codes: H10N 50/01 Manufacture or treatment
• CPC Class Codes: H10N 50/10 Magnetoresistive devices
• CPC Class Codes: Y10S 977/933 Spintronics or quantum computing
• CPC Class Codes: Y10S 977/935 Spin dependent tunnel, SDT, junction, e.g. tunneling magnetoresistance, TMR

Abstract

A particular magnetic tunnel junction (MTJ) cell includes a side wall defining a first magnetic domain adapted to store a first digital value. The MTJ cell also includes a bottom wall coupled to the side wall and defining a second magnetic domain adapted to store a second digital value.

Claims

1. A magnetic tunnel junction (MTJ) cell comprising:

a side wall defining a first magnetic domain adapted to store a first digital value; and

a bottom wall coupled to the side wall and defining a second magnetic domain adapted to store a second digital value.

2. The MTJ cell of claim 1, further comprising a second side wall defining a third magnetic domain adapted to store a third digital value.

3. The MTJ cell of claim 2, wherein the side wall is substantially parallel to the second side wall.

4. The MTJ cell of claim 3, wherein side wall is separated from the second side wall by a distance that is less than a height of the side wall.

5. The MTJ cell of claim 2, wherein the side wall is substantially perpendicular to the second side wall.

6. The MTJ cell of claim 2, further comprising a third side wall defining a fourth magnetic domain adapted to store a fourth digital value.

7. The MTJ cell of claim 6, further comprising a fourth side wall defining a fifth magnetic domain adapted to store a fifth digital value.

8. The MTJ cell of claim 7, wherein the MTJ cell is U-shaped.

9. The MTJ cell of claim 1, wherein the side wall has a rectangular shape.

10. A memory device comprising:

a magnetic tunnel junction (MTJ) cell comprising;

a side wall defining a first magnetic domain adapted to store a first digital value; and

a bottom wall coupled to the side wall and defining a second magnetic domain adapted to store a second digital value.

11. The memory device of claim 10, further comprising:

a first terminal coupled to the MTJ cell; and

a first transistor coupled to the first terminal and coupled to a data write line and to a first source line.

12. The memory device of claim 11, further comprising:

a second terminal coupled to the MTJ cell; and

a second transistor coupled to the second terminal and coupled to the data write line and to a second source line.

13. The memory device of claim 12, wherein the first terminal is coupled to the side wall and wherein the second terminal is coupled to the bottom wall.

14. The memory device of claim 12, further comprising a third terminal coupled to the MTJ cell and to a bit line.

15. The memory device of claim 10, wherein the MTJ cell further comprises a second side wall substantially parallel to the side wall and defining a third magnetic domain adapted to store a third value.

16. The memory device of claim 15, further comprising a center electrode extending between the side wall and the second side wall.

17. The memory device of claim 15, further comprising a third side wall defining a fourth magnetic domain adapted to store a fourth digital value.

18. The memory device of claim 17, further comprising a fourth side wall and defining a fifth magnetic domain adapted to store a fifth digital value.

19. The memory device of claim 18, wherein the fourth side wall is substantially parallel to the third side wall.

20. A method comprising:

selectively activating a bit line coupled to a center electrode of a magnetic tunnel junction (MTJ) structure including a plurality of side walls, each of the plurality of sidewalls including a free layer to carry a unique vertical magnetic domain; and

selectively activating one or more bidirectional switches to enable current to flow through the MTJ structure, wherein each of the one or more bi-directional switches is coupled to a respective side wall of the plurality of side walls and to a power source.

21. The method of claim 20, further comprising, during a read operation, determining a data value associated with each of the unique vertical magnetic domains based on a resistance associated with a current path through the MTJ structure.

22. The method of claim 20, further comprising, during a write operation, selectively controlling magnetic directions within free layers of selected magnetic domains, the magnetic directions associated with data values.