WAFER LEVEL PACKAGED MEMS DEVICE

• US 20110092018A1
• Filed: 12/10/2010
• Published: 04/21/2011
• Est. Priority Date: 09/28/2007
• Status: Active Grant

• Current Assignee: Honeywell International Inc.
• Original Assignee: Honeywell International Inc.
• Inventors: LaFond, Peter H., Yu, Lianzhong
• Granted Patent: US 8,685,776 B2
• Time in Patent Office: Days
• US Class Current: 438/106
• CPC Class Codes: A01B 1/02 Spades; Shovels hand-operated dredgers E02F3/02
• CPC Class Codes: A01B 1/026 with auxiliary handles for facilitating lifting
• CPC Class Codes: B81C 1/00333 Aspects relating to packaging of MEMS devices, not covered by groups B81C1/00269 - B81C1/00325
• CPC Class Codes: B81C 2203/0118 Bonding a wafer on the substrate, i.e. where the cap consists of another wafer
• CPC Class Codes: B81C 2203/036 Fusion bonding

Abstract

An apparatus and method for sensor architecture based on bulk machining of silicon wafers and fusion bond joining which provides a nearly all-silicon, hermetically sealed, microelectromechanical system (MEMS) device. An example device includes a device sensor mechanism formed in an active semiconductor layer and separated from a handle layer by a dielectric layer, and a silicon cover plate having a handle layer with a dielectric layer being bonded to portions of the active layer. Pit are included in one of the handle layers and corresponding dielectric layers to access electrical leads on the active layer. Another example includes set backs from the active components formed by anisotropically etching the handle layer while the active layer has been protectively doped.

Claims

1. A method for forming a wafer level package device, the method comprising:

etching at least one active component in an active layer of a base silicon-on-insulator (SOI) wafer, the SOI wafer having a handle layer separated from the active layer by a dielectric layer;

etching the dielectric layer in the vicinity of the formed active component after etching of the at least one active component;

etching a dielectric layer of a cover plate wafer to form cavities to coincide with the at least one active components, the cover plate having a handle layer attached to the cover plate wafer dielectric layer,

etching at least one of the handle layers and corresponding dielectric layer to expose a portion of the surface of the active layer; and

forming a metallization on a portion of the exposed surface of the active layer,

wherein the at least one active component is included within a cavity.

2. The method of claim 1, further comprising etching at least one isolator flange into the base wafer and the cover plate wafer at an exterior edge.

3. The method of claim 1, wherein the cavity is a hermetically sealed cavity.

4. The method of claim 3, wherein the cavity is defined by the handle layers on two sides and the active layer and the dielectric layers on all other sides.

5. A method for forming a wafer level package device, the method comprising:

forming at least one active component in an active layer of a base silicon-on-insulator (SOI) wafer;

applying a dopant to the active layer;

anisotropically etching a handle layer of the SOI wafer in the vicinity of the at least one active component;

etching an active layer and a dielectric layer of a cover plate SOI wafer to form one or more cavities to coincide with the active components of the base wafer;

bonding the SOI wafer to the cover plate SOI wafer;

etching at least one of the handle layers and corresponding dielectric layer to expose the surface of the corresponding active layer from the base SOI wafer or from the cover plate SOI wafer; and

forming a metallization on at least a portion of the exposed active layer,

wherein the at least one active component is included within a cavity.

6. The method of claim 5, further comprising etching the SOI wafers in order to form one or more isolation flanges.

7. The method of claim 5, wherein the cavity is a hermetically sealed cavity.

8. The method of claim 7, wherein the cavity is defined by the handle layers on two sides and the active layer and the dielectric layers on all other sides.