Transistor Gate Forming Methods and Transistor Structures

• US 20110092062A1
• Filed: 12/23/2010
• Published: 04/21/2011
• Est. Priority Date: 09/01/2005
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Tang, Sanh D., Haller, Gordon A., Raghu, Prashant, Iyer, Ravi
• Granted Patent: US 8,349,687 B2
• Time in Patent Office: Days
• US Class Current: 438/589
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66787 with a gate at the side of the channel
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A transistor gate forming method includes forming a metal layer within a line opening and forming a fill layer within the opening over the metal layer. The fill layer is substantially selectively etchable with respect to the metal layer. A transistor structure includes a line opening, a dielectric layer within the opening, a metal layer over the dielectric layer within the opening, and a fill layer over the metal layer within the opening. The metal layer/fill layer combination exhibits less intrinsic less than would otherwise exist if the fill layer were replaced by an increased thickness of the metal layer. The inventions apply at least to 3-D transistor structures.

Claims

1. A transistor gate forming method comprising:

forming a gate metal layer within a gate line opening extending into a semiconductive substrate;

forming a gate fill layer within the opening over the metal layer, the fill layer exhibiting the property of being substantially selectively etchable with respect to the metal layer; and

removing a portion of the fill layer at a selectivity ratio of at least 2 to 1 with respect to the metal layer.

2. The method of claim 1 wherein the opening is a word line trench.

3. The method of claim 1 wherein the opening is a RAD opening laterally surrounding a source/drain pillar between opposing source/drain walls.

4. The method of claim 1 wherein the metal layer exhibits the property of being substantially selectively etchable with respect to the fill layer and further comprising removing a portion of the metal layer at a selectivity ratio of at least 2 to 1 with respect to the fill layer.

5. The method of claim 1 wherein the metal layer comprises titanium nitride.

6. The method of claim 1 wherein the fill layer is semiconductive or conductive.

7. The method of claim 1 wherein forming the fill layer comprises covering the metal layer, at least within the opening, with the fill layer.

8. The method of claim 1 wherein a thickness of the fill layer within the opening is greater than a thickness of the metal layer.

9. The method of claim 1 wherein forming the fill layer comprises filling all of the opening over the metal layer.

10. The method of claim 1 wherein the fill layer comprises polysilicon.

11. The method of claim 1 wherein the fill layer exhibits a porosity greater than a porosity of the metal layer.

12. The method of claim 1 wherein removing the portion of the fill layer occurs at a selectivity ratio of at least 5 to 1 with respect to the metal layer.

13-15. -15. (canceled)

16. A transistor gate forming method comprising:

forming a gate metal layer containing titanium nitride within a gate line opening extending into a semiconductive substrate;

filling all of the opening over the metal layer with a gate fill layer containing polysilicon, a thickness of the fill layer within the opening being greater than a thickness of the metal layer, the fill layer exhibiting the property of being substantially selectively etchable with respect to the metal layer, the metal layer exhibiting the property of being substantially selectively etchable with respect to the fill layer;

removing a portion of the fill layer at a selectivity ratio of at least 2 to 1 with respect to the metal layer; and

removing a portion of the metal layer at a selectivity ratio of at least 2 to 1 with respect to the fill layer,

17. The method of claim 16 wherein the opening is a word line trench.

18. The method of claim 16 wherein the opening is a RAD opening laterally surrounding a source/drain pillar between opposing source/drain walls.

19. A transistor gate forming method comprising:

forming a gate line opening extending into a semiconductive substrate, the opening having a semiconductive bottom and semiconductive side walls;

forming a gate dielectric layer within the opening over the semiconductive side walls and semiconductive bottom, the dielectric layer having an insulative bottom and insulative side walls;

forming a gate metal layer within the opening over the insulative bottom and insulative side walls, the metal layer having a conductive bottom and conductive side walls;

forming a gate fill layer within the opening over the conductive bottom and conductive side walls; and

removing excess fill layer substantially selectively with respect to the metal layer at a selectivity ratio of at least 2 to 1 while exposing a portion of the metal layer under the fill layer without exposing the dielectric layer under the metal layer.

20. The method of claim 19 wherein the opening is a word line trench, the metal layer ultimately extending fully up the opening side walls.

21. The method of claim 19 wherein the opening is a RAD opening laterally surrounding a source/drain pillar between opposing source/drain walls, the metal layer ultimately extending only partially up the opening side walls.

22. The method of claim 19 further comprising removing the exposed portion of the metal layer substantially selectively with respect to the fill layer at a selectivity ratio of at least 2 to 1.

23. The method of claim 22 wherein removing the exposed portion of the metal layer occurs at a selectivity ratio of at least 5 to 1 .

24. The method of claim 19 wherein the metal layer comprises titanium nitride.

25. The method of claim 19 wherein the fill layer is semiconductive or conductive.

26. The method of claim 19 wherein forming the fill layer comprises covering the metal layer, at least within the opening, with the fill layer.

27. The method of claim 19 wherein a thickness of the fill layer within the opening is greater than a thickness of the metal layer.

28. The method of claim 19 wherein forming the fill layer comprises filling all of the opening over the metal layer.

29. The method of claim 19 wherein the fill layer comprises polysilicon.

30. The method of claim 19 wherein the fill layer exhibits a porosity greater than a porosity of the metal layer.

32. The method of claim 19 wherein removing the excess fill layer occurs at a selectivity ratio of at least 5 to 1.

31. (canceled)

33-54. -54. (canceled)