Switch Circuit and Method of Switching Radio Frequency Signals

• US 20110092179A1
• Filed: 12/28/2010
• Published: 04/21/2011
• Est. Priority Date: 10/10/2001
• Status: Active Grant

• Current Assignee: pSemi Corporation (Murata Manufacturing Co Limited)
• Original Assignee: Peregrine Semiconductor Corporation (Murata Manufacturing Co Limited)
• Inventors: Cable, James S., Burgener, Mark L.
• Granted Patent: US 8,583,111 B2
• Time in Patent Office: Days
• US Class Current: 455/333
• CPC Class Codes: H01P 1/15 by semiconductor devices
• CPC Class Codes: H03K 17/063 in field-effect transistor switches
• CPC Class Codes: H03K 17/102 in field-effect transistor switches
• CPC Class Codes: H03K 17/6871 the output circuit comprising more than one controlled field-effect transistor
• CPC Class Codes: H03K 17/693 Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors logic circuits H03K19/00; code converters H03M5/00, H03M7/00
• CPC Class Codes: H03K 19/018521 of complementary type, e.g. CMOS
• CPC Class Codes: H03K 19/0944 using MOSFET or insulated gate field-effect transistors, i.e. IGFETH03K19/096 takes precedence
• CPC Class Codes: H03K 2017/0803 against radiation hardening
• CPC Class Codes: H04B 1/40 Circuits

Abstract

An RF switch circuit and method for switching RF signals that may be fabricated using common integrated circuit materials such as silicon, particularly using insulating substrate technologies. The RF switch includes switching and shunting transistor groupings to alternatively couple RF input signals to a common RF node, each controlled by a switching control voltage (SW) or its inverse (SW_), which are approximately symmetrical about ground. The transistor groupings each comprise one or more insulating gate FET transistors connected together in a “stacked” series channel configuration, which increases the breakdown voltage across the series connected transistors and improves RF switch compression. A fully integrated RF switch is described including control logic and a negative voltage generator with the RF switch elements. In one embodiment, the fully integrated RF switch includes an oscillator, a charge pump, CMOS logic circuitry, level-shifting and voltage divider circuits, and an RF buffer circuit.

Claims

1. A switch circuit, comprising:

a) a first port means for outputting or receiving a first signal;

b) a second port means for outputting or receiving a second signal;

c) a common port means;

d) a first switch transistor grouping means having a first node coupled to the first port means and a second node coupled to the common port means, wherein the first switch transistor grouping means is controlled by a first switch control signal (SW);

e) a second switch transistor grouping means having a first node coupled to the second port means and a second node coupled to the common port means, wherein the second switch transistor grouping means is controlled by a second switch control signal (SW_);

f) a first shunt transistor grouping means having a first node coupled to the first port means and a second node coupled to ground, wherein the first shunt transistor grouping means is controlled by the second switch control signal (SW_); and

g) a second shunt transistor grouping means having a first node coupled to the second port means and a second node coupled to ground, wherein the second shunt transistor grouping means is controlled by the first switch control signal (SW);

wherein when the first control signal SW is enabled the first switch transistor grouping means is enabled and the first shunt transistor grouping means is disabled thereby coupling the first port means to the common port means, and the second shunt transistor grouping means is enabled and the second switch transistor grouping means is disabled thereby shunting the second port means to ground, and wherein when the second control signal SW_ is enabled the second switch transistor grouping means is enabled and the second shunt transistor grouping means is disabled thereby coupling the second port means to the common port means, and the first shunt transistor grouping means is enabled and the first switch transistor grouping means is disabled thereby shunting the first port means to ground.

2. The switch circuit of claim 1, wherein the first and second switch transistor grouping means comprise a single MOSFET, and wherein the first and second shunt transistor grouping means comprise a single MOSFET.

3. The switch circuit of claim 1, wherein the first and second switch transistor grouping means comprise a plurality of MOSFETs arranged in a stacked configuration, and wherein the first and second shunt transistor grouping means comprise a plurality of MOSFETs arranged in a stacked configuration.

4. The switch circuit of claim 1, wherein the first and the second switch transistor grouping means comprise a first number of MOSFETs arranged in a stacked configuration, and wherein the first and second shunt transistor grouping means comprise a second number of MOSFETs arranged in a stacked configuration, and wherein the first number and the second number of MOSFETs differ.

5. A method of switching RF signals, comprising:

(a) receiving or outputting a first RF signal (RF1) via a first RF port;

(b) receiving or outputting a second RF signal (RF2) via a second RF port;

(c) providing an RF common port;

(d) controlling a first switch transistor grouping having a first node coupled to the first RF port and a second node coupled to the RF common port;

(e) controlling a second switch transistor grouping having a first node coupled to the second RF port and a second node coupled to the RF common port;

(f) controlling a first shunt transistor grouping having a first node coupled to the first RF port and a second node coupled to ground; and

(g) controlling a second shunt transistor grouping having a first node coupled to the second port and a second node coupled to ground;

wherein the first switch and second shunt transistor groupings are enabled while the second switch and first shunt transistor groupings are disabled, thereby coupling the first RF port with the RF common port and shunting the second RF port to ground, and wherein the second switch and first shunt transistor groupings are enabled while the first switch and second shunt transistor groupings are disabled, thereby coupling the second RF port with the RF common port and shunting the first RF port to ground.