Memory Controller With Ring Bus for Interconnecting Memory Clients to Memory Devices

• US 20110093644A1
• Filed: 11/11/2010
• Published: 04/21/2011
• Est. Priority Date: 07/11/2006
• Status: Abandoned Application

• Current Assignee: Alexander Miretsky, Patrick Law, Warren F. Kruger
• Original Assignee: Alexander Miretsky, Patrick Law, Warren F. Kruger
• Inventors: Miretsky, Alexander, Kruger, Warren F., Law, Patrick
• Application Number:
  US12/944,660
• Publication Number:
  US 20110093644A1
• Time in Patent Office: Days
• US Class Current: 710/316
• CPC Class Codes: G06F 13/1657 Access to multiple memories

Abstract

Embodiments of a distributed memory controller system implemented on a single integrated circuit device are described. In one embodiment, a memory controller that provides an interconnection circuit between a first plurality of memory devices to a second plurality of memory clients includes a ring bus to route at least one of the memory request and data return signals between the memory clients and the memory devices. The ring bus is configured in a ring topography that is distributed across a portion of an integrated circuit device, resulting in a reduction in the maximum wiring density at the center of memory controller. The ring bus structure also reduces the overall number of interconnections as well as the number of storage elements, thus reducing the total area used by the memory controller. The ring bus couples memory clients that are physically located within the ring topography on the integrated circuit to external memory devices through memory device interface circuits located on the integrated circuit device. The memory controller also includes deadlock avoidance mechanisms that utilize virtual channels on the ring bus for one or more defined types of bus traffic.

Claims

1. An integrated circuit device comprising:

a plurality of memory control circuits, each memory control circuit includes a memory interface providing access to one or more memory devices separate from the integrated circuit;

a memory client operable to send or receive data to the memory devices by sending memory access requests to the memory control circuits; and

a bus interconnecting the memory control circuits in a topography distributed around the integrated circuit.

2. The integrated circuit device of claim 1, wherein the bus comprises a plurality of segments, and wherein each segment interconnects a pair of memory control circuits together.

3. (canceled)

4. The integrated circuit device of claim 3, wherein the bus comprises a ring bus.

5. The integrated circuit device of claim 4, wherein

the memory client is configured to transmit a read request signal to a target memory device and receive a data read signal from the target memory device in response to the read request signal from the memory client;

and

the memory client is configured to transmit a write request signal to the target memory device and receive a write acknowledge signal from the target memory device in response to the write request signal from the memory client.

6. The integrated circuit device of claim 5, wherein the ring bus is used to transmit the read data signal from the target memory device to the memory client.

7. The integrated circuit device of claim 6, wherein the ring bus is used to transmit the read request signal from the memory client to the target memory device.

8. The integrated circuit device of claim 7, wherein the ring bus is used to transmit the write request signal from the memory client to the target memory device.

9. The integrated circuit device of claim 8, wherein the ring bus is used to transmit the write acknowledge signal from the target memory device to the memory client.

10. The integrated circuit device of claim 9, wherein the ring bus comprises a respective virtual channel for each of the read data, read request, write request and write acknowledge signals to avoid deadlock among each of the read data, read request, write request, and write acknowledge signal types.

11. The integrated circuit device of claim 10, wherein each of the read data, read request, write request, and write acknowledge signal types comprises a high-priority traffic type and a low-priority traffic type, and wherein each virtual channel comprises a respective sub-channel for each of the high-priority and low-priority traffic type of each signal type.

12. The integrated circuit device of claim 9, wherein the ring bus includes a virtual channel denoted a next ring stop channel for high priority traffic of each signal type, and wherein the next ring stop channel utilizes reserved buffer space within one or more ring bus components.

13. The integrated circuit device of claim 5 further comprising a central switch matrix coupled between the memory client and the target memory device, to transmit the read request from the memory client to the target memory device.

14. The integrated circuit device of claim 5, wherein the ring bus comprises two counter rotating transmission lines.

15. A memory controller coupling a plurality of memory clients on an integrated circuit device to external memory devices, comprising:

a plurality of read bus switches, each read bus switch of the plurality of read bus switches coupled to a respective memory device of the external memory devices;

one or more of the memory clients coupled to at least one read bus switch, and configured to transmit a memory request to a target memory device and receive a memory read transfer from the target memory device in response to the memory request;

a central memory controller circuit coupled to at least one read bus switch and each of the one or more memory clients, and configured to route the memory request to the target memory device;

a ring bus connected between pairs of read bus switches of the plurality of read bus switches, and configured to transmit the memory read transfer between the target memory device and a requesting memory client;

an arbiter circuit coupling each memory client of the one or more memory clients to a respective memory channel;

a sequencer circuit coupling each arbiter to a respective read bus switch corresponding to the requesting memory client; and

a client interface coupling the arbiter circuit to the requesting memory client and configured to implement a flow control protocol for the requesting memory client.

17. The memory controller of claim 15, wherein the ring bus comprises a counter rotating ring bus coupling all of the plurality of read bus switches together in a ring topography.

18. The memory controller of claim 17, wherein the memory control circuit comprises a switch matrix configured to transmit the memory requests from the requesting memory client to the target memory.

19. The memory controller of claim 18 wherein each memory device represents a dynamic random access memory channel, the memory controller device further comprising:

an arbiter circuit coupling each memory client of the one or more memory clients to a respective memory channel;

a sequencer circuit coupling each arbiter to a respective read bus switch corresponding to the requesting memory client; and

a client interface coupling the arbiter circuit to the requesting memory client and configured to implement a flow control protocol for the requesting memory client.

16. The memory controller of 15, wherein each respective memory device comprises a dynamic random access memory.

20. An integrated circuit device including a memory control circuit, the integrated circuit device comprising:

a plurality of read bus switches, each read bus switch of the plurality of read bus switches coupled to a respective memory device located off of the integrated circuit device;

one or more memory clients coupled to each read bus switch of the plurality of read bus switches, and configured to transmit a memory request to a target memory device and receive a memory read transfer from the target memory device in response to the memory request; and

a ring bus connected between pairs of read bus switches of the plurality of read bus switches, and configured to transmit both memory requests from a requesting client to a target memory device, and memory read transfers between the target memory device and the requesting memory client;

wherein each read bus switch comprises,

a ring stop circuit configured to receive incoming read and write data traffic from adjacent ring stop circuits on the ring bus;

an arbiter circuit coupling the ring stop circuit to a respective memory channel;

a sequencer circuit coupling each arbiter to the respective memory channel; and

a client interface coupling the ring stop circuit to the requesting memory client and configured to implement a flow control protocol for the requesting memory client.

21. The integrated circuit device of claim 20, wherein the ring bus comprises a counter rotating ring bus coupling all of the plurality of read bus switches together in a ring topography.

22. The integrated circuit device of claim 21 wherein each memory device represents a dynamic random access memory channel.

23. (canceled)

24. The integrated circuit device of claim 23, wherein read and write data traffic is organized using input and output queues in the ring stop circuit, and wherein input and output queues are prioritized depending in one of low priority and high priority data types.

25. The integrated circuit device of claim 24, wherein the arbiter circuit is configured to arbitrate data of the same priority using a round-robin algorithm.

26. A memory controller coupling a plurality of memory clients on an integrated circuit device to a plurality of memory devices, comprising:

a plurality of ring bus stops, each coupled to a respective memory device of the plurality of memory devices;

a memory controller circuit coupled to at least one ring bus stop and each of the plurality of memory clients, and configured to route memory access signals between the plurality of memory clients and memory devices;

a ring bus connected between pairs of ring bus stops, and configured to physically transmit the memory access signals between the plurality of memory clients and memory devices; and

a deadlock avoidance circuit configured to prevent deadlock of the memory access signals on the ring bus.

27. The memory controller of claim 26, wherein the memory access signals comprise types consisting of:

read requests, write acknowledgments, read returns, and write requests.

28. The memory controller of claim 27, wherein the deadlock comprises read/write deadlock caused by two or more types of memory access signals sharing same physical channel of the ring bus.

29. The memory controller of claim 28, wherein the deadlock avoidance circuit comprises a virtual channel for each of the memory access signal types.

30. The memory controller of claim 27, wherein the deadlock comprises multi-hop deadlock caused by filling an input buffer of a ring bus stop with transactions of any memory access signal type.

31. The memory controller of claim 30, wherein the deadlock avoidance circuit comprises a next ring stop virtual channel for each ring bus stop and one or more reserved buffer entries in an input buffer of each ring bus stop.

32. The memory controller of claim 31, wherein a subset of memory access signals are designated as next ring stop traffic, and wherein the next ring stop traffic is temporarily stored in the reserved buffer entries when the input buffer exceeds a predetermined storage level.