MEMORY HAVING INTERNAL PROCESSORS AND DATA COMMUNICATION METHODS IN MEMORY

• US 20110093662A1
• Filed: 10/21/2009
• Published: 04/21/2011
• Est. Priority Date: 10/21/2009
• Status: Active Grant

• Current Assignee: Lodestar Licensing Group LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Merritt, Todd A., Pawlowski, J. Thomas, Skinner, Dan, Walker, Robert M.
• Granted Patent: US 9,477,636 B2
• Time in Patent Office: Days
• US Class Current: 711/147
• CPC Class Codes: G06F 12/0813 with a network or matrix configuration
• CPC Class Codes: G06F 13/1673 using buffers
• CPC Class Codes: G06F 13/4068 Electrical coupling
• CPC Class Codes: G06F 15/7821 Tightly coupled to memory, e.g. computational memory, smart memory, processor in memory
• CPC Class Codes: G06F 3/0613 in relation to throughput
• CPC Class Codes: G06F 3/0625 Power saving in storage systems
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/067 Distributed or networked storage systems, e.g. storage area networks [SAN], network attached storage [NAS]
• CPC Class Codes: G06F 3/0683 Plurality of storage devices
• CPC Class Codes: G06F 9/3001 Arithmetic instructions
• CPC Class Codes: G06F 9/30043 LOAD or STORE instructions; Clear instruction

Abstract

Memory having internal processors, and methods of data communication within such a memory are provided. In one embodiment, an internal processor may concurrently access one or more banks on a memory array on a memory device via one or more buffers. The internal processor may be coupled to a buffer capable of accessing more than one bank, or coupled to more than one buffer that may each access a bank, such that data may be retrieved from and stored in different banks concurrently. Further, the memory device may be configured for communication between one or more internal processors through couplings between memory components, such as buffers coupled to each of the internal processors. Therefore, a multi-operation instruction may be performed by different internal processors, and data (such as intermediate results) from one internal processor may be transferred to another internal processor of the memory, enabling parallel execution of an instruction(s).

Claims

1. A memory comprising:

a plurality of memory components;

an internal processor configured to execute at least part of an instruction, wherein the internal processor is coupled to at least one of the memory components; and

a memory array configured to store information, wherein each of the memory components is operably coupled to a respective at least one group of memory cells of the memory array.

2. The memory, as set forth in claim 1, wherein the internal processor is coupled to more than one memory component.

3. The memory, as set forth in claim 2, wherein the more than one memory component comprises a first buffer bussed to a first bank of the memory array and a second buffer bussed to a second bank of the memory array.

4. The memory, as set forth in claim 3, wherein the memory is configured to retrieve information from the first bank via the first buffer and store results to the second bank via the second buffer substantially simultaneously.

5. The memory, as set forth in claim 2, wherein a first memory component of the more than one memory components coupled to the internal processor is coupled to a second memory component of the more than one memory components coupled to a second internal processor.

6. The memory, as set forth in claim 5, wherein intermediate results of an operation performed by the first internal processor is transferrable for an operation to be performed by the second internal processor through the coupling between the first memory component and the second memory component.

7. The memory, as set forth in claim 1, wherein the memory component is a buffer.

8. The memory, as set forth in claim 1, wherein the memory component is a register.

9. The memory, as set forth in claim 1, wherein the internal processor comprises a compute engine.

10. The memory, as set forth in claim 1, wherein the internal processor comprises a plurality of compute engines.

11. The memory, as set forth in claim 1, wherein the internal processor is one or a plurality of internal processors of the memory.

12. The memory, as set forth in claim 1, wherein the memory comprises a memory device.

13. The memory, as set forth in claim 1, wherein the memory comprises a memory system.

14. The memory, as set forth in claim 1, wherein the memory comprises a multi-chip package including a first die having the memory array and a second die having the internal processor.

15. The memory, as set forth in claim 1, wherein the internal processor is embedded on a memory device that includes the memory array.

16. The memory, as set forth in claim 1, wherein the group of memory cells comprises a bank of the memory array.

17. The memory, as set forth in claim 1, wherein the internal processor comprises a plurality of compute engines.

18. The memory, as set forth in claim 1, wherein each of the memory components is capable of communicating with a plurality of memory banks.

19. The memory, as set forth in claim 1, wherein the internal processor is capable of communicating with another internal processor of the memory.

20. The memory, as set forth in claim 1, further comprising an external processor configured to substantially control the internal processor.

21. The memory, as set forth in claim 1, further comprising an external processor configured to substantially control access to the memory.

22. The memory, as set forth in claim 1, wherein the internal processor is configured to execute instructions, wherein executing instructions comprises performing one or more operations.

23. A memory comprising:

an internal processor configured to execute at least part of an instruction;

a memory component coupled to the internal processor and configured to store data for the at least part of an instruction and results of the executed at least part of an instruction; and

a memory array comprising a first group of memory cells and a second group of memory cells, wherein the memory component is capable of accessing both the first group and the second group.

24. The memory, as set forth in claim 23, wherein executing at least part of an instruction comprises performing an operation.

25. The memory, as set forth in claim 23, wherein the first group and the second group are coupled via a bidirectional bus.

26. The memory, as set forth in claim 23, wherein the memory component is capable of accessing the first group via a first bus between the memory component and the first group, and wherein the memory component is capable of accessing the second group via a second bus between the memory component and the second group.

27. The memory, as set forth in claim 26, wherein the memory is configured to substantially simultaneously transfer information between the first group and the memory component and transfer information between the second group and the memory component.

28. The memory, as set forth in claim 23, wherein the memory component comprises a buffer of a plurality of buffers, each coupled to one or more internal processors of a plurality of internal processors, wherein at least one of the plurality of buffers is coupled to another at least one of the plurality of buffers.

29. A memory comprising:

a memory array; and

a first internal processor configured to execute at least part of an instruction on data to produce results, wherein the data is transferrable from the memory array and transferrable from a second internal processor, and wherein the results are transferrable to a third internal processor and transferrable to the memory array.

30. The memory, as set forth in claim 29, wherein the data is transferrable from a first bank in the memory array, and wherein the results are transferrable to a second bank in the memory array.

31. The memory, as set forth in claim 29, wherein the data is transferrable from a first buffer bussed to a first bank in the memory array, and wherein the results are transferrable to a second buffer bussed to a second bank in the memory array.

32. The memory, as set forth in claim 29, wherein the second internal processor is configured to execute at least part of an instruction to produce the data for the first internal processor, and wherein the data is transferrable from the second internal processor to the first internal processor through a bus between a first buffer coupled to the first internal processor and a second buffer coupled to the second internal processor.

33. The memory, as set forth in claim 29, wherein the results are transferrable to a third internal processor through a bus between a first buffer coupled to the first internal processor and a third buffer coupled to the third internal processor.

34. The memory, as set forth in claim 29, comprising a first buffer and a second buffer, wherein both the first and second buffers are coupled to the first internal processor, and wherein data and results are transferable via a bus between the first buffer and the second buffer.

35. A method of communication in a memory, wherein the method comprises:

designating a first internal processor of the memory to perform an operation;

performing the operation at the first internal processor of the plurality to produce a first result;

transferring the first result from the first internal processor to a second internal processor via a coupling between a first memory component coupled to the first internal processor and a second memory component coupled to the second internal processor; and

performing an operation at the second internal processor to produce a second result.

36. The method, as set forth in claim 35, comprising:

transferring data from a first memory bank of a memory array to the first internal processor, and wherein performing the operation at the first internal processor comprises performing the operation on the data; and

transferring the second result from the second internal processor to a second memory bank of the memory array.

37. The method, as set forth in claim 36, wherein transferring the data from the first memory bank and transferring the second result to the second memory bank occur substantially simultaneously.

38. The method, as set forth in claim 36, wherein transferring the data from the first memory bank comprises transferring the data from the first memory bank via a memory component coupled to the first internal processor.

39. The method, as set forth in claim 36, wherein transferring the data from the second internal processor to the second memory bank comprises transferring the data from the second internal processor via a memory component coupled to the second internal processor.