Memory System and Method for Two Step Memory Write Operations

• US 20110093669A1
• Filed: 12/21/2010
• Published: 04/21/2011
• Est. Priority Date: 10/10/1997
• Status: Active Grant

• Current Assignee: Craig E. Hampel, Frederick A. Ware, Paul G. Davis
• Original Assignee: Craig E. Hampel, Frederick A. Ware, Paul G. Davis
• Inventors: Hampel, Craig E., Ware, Frederick A., Davis, Paul G.
• Granted Patent: US 8,140,805 B2
• Time in Patent Office: Days
• US Class Current: 711/154
• CPC Class Codes: G06F 13/1626 by reordering requests
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 2207/2218 Late write
• CPC Class Codes: G11C 2207/229 Timing of a write operation sense amplifier timing G11C7/06, G11C7/08
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1039 using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management

Abstract

A method of operating a memory component that includes a memory core includes receiving, from external control lines, a write command that specifies a write operation. The write command is stored for a first time period after receiving the write command. After the first time period, the write operation is initiated in response to the write command. During the write operation, unmasked portions of received data are written to the memory core, where the unmasked portions of the data are bits of the data that are identified by received mask information as not being masked.

Claims

1. A memory system, comprising:

a communication channel coupled to a controller and coupled to a memory device;

the controller to generate control information and data information, including at least two write commands to the memory device followed by another command and then followed by a read command to the memory device, wherein respective data information corresponds to respective control information, the other command is between the at least two write commands and the read command; and

the memory device to receive the control information and the data information in a same order as generated by the controller and to process the read command prior to completing the processing of one of the at least two write commands.