Multi-Threaded Processors and Multi-Processor Systems Comprising Shared Resources

• US 20110093857A1
• Filed: 10/20/2009
• Published: 04/21/2011
• Est. Priority Date: 10/20/2009
• Status: Active Grant

• Current Assignee: Maxlinear Incorporated
• Original Assignee: Infineon Technologies AG
• Inventors: Fenzl, Gunther, Sydow, Carsten
• Granted Patent: US 8,695,002 B2
• Time in Patent Office: Days
• US Class Current: 718/102
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming

Abstract

An apparatus is provided comprising at least two processing entities. Shared resources are usable by a first and a second processing entity. A use of the shared resources is detected, and the execution of instructions associated with said processing entities is controlled based on the detection.

Claims

1. A data processing apparatus, comprising:

a first processing entity,

a second processing entity,

shared resources usable by said first processing entity and by said second processing entity,

wherein said apparatus is configured to detect a use of shared resources by said first processing entity and said second processing entity and control execution of instructions associated with said first processing entity and said second processing entity based on said detection.

2. The apparatus of claim 1,

wherein said apparatus is configured as a multi-threaded processor core, and

wherein each of said first processing entity and said second processing entity comprises a respective thread context.

3. The apparatus of claim 1,

wherein said shared resources comprise one or more elements selected from the group consisting of a Fill Store Buffer, a buffer, a level 1 data cache, a level 1 instruction cache, a level 2 cache, a level 3 cache, a Multiply Divide Unit, an Arithmetic Logic Unit, a memory or a memory controller.

4. The apparatus of claim 1,

further comprising a scheduler to assign time slots for instruction execution to said first processing entity and said second processing entity, said apparatus being configured to control said scheduler based on said detected use of shared resources.

5. The apparatus of claim 1,

comprising a hardware portion to detect said use of shared resources.

6. The apparatus of claim 1,

further comprising a software portion to control said execution.

7. The apparatus of claim 1,

further comprising a firmware portion to detect a reduced possibility of a processing entity to access shared resources.

8. The apparatus of claim 1,

wherein said first processing entity and said second processing entity each are selected from the group consisting of a processor core and a processor.

9. A multi-threaded processor core comprising:

a first thread context associated with the execution of a first thread,

a second thread context associated with the execution of a second thread,

a scheduler to assign time slots for execution of said first thread and said second thread,

shared resources usable both for execution of said first thread and execution of said second thread, and

a hardware unit configured to detect use of said shared resources by said first thread and said second thread.

10. The processor core of claim 9,

wherein said hardware unit is coupled directly to said scheduler, said scheduler being configured to modify said assignment of time slots based on signals received from said hardware unit.

11. The processor core of claim 9,

further comprising executable software to evaluate signals received from said hardware unit and to control said scheduler based on said received signals.

12. The processor core of claim 11,

further comprising firmware associated with said second thread context, said firmware being configured to periodically execute test instructions and to report irregularities in said execution to said executable software.

13. The processor core of claim 11,

wherein said executable software is run periodically.

14. The processor core of claim 11,

wherein said executable software is run on a third thread context.

15. The processor core of claim 9,

wherein said second thread is a real-time thread.

16. The processor core of claim 15,

wherein said real-time thread is associated with one of the groups consisting of voice processing and video processing.

17. The processor core of claim 9,

wherein said first thread is associated with running an operating system.

18. The processor core of claim 9,

wherein said shared resources comprise one or more elements selected from the group consisting of a Fill Store Buffer, a buffer, a level 1 data cache, a level 1 instruction cache, a Multiply Divide Unit and an Arithmetic Logic Unit.

19. The processor core of claim 9,

wherein said hardware unit is configured to check one or more parameters selected from the group consisting of a number of instructions said first context executes in a time interval, a number of instructions said second thread context executes in a time interval, a number of Fill Store Buffer entries said first thread context uses, a number of Fill Store Buffer entries said second thread context uses, a number of stalls said first thread context produces, a number of stalls said second thread context produces, a number of instruction cache accesses said first thread context produces, a number of instruction cache accesses said second thread context produces, a number of data cache accesses said second thread context produces, a number of data cache accesses said second thread context produces, a number of cache misses per time interval said first thread context produces, a number of cache misses per time interval said second thread context produces, an occupation of a Multiply Divide Unit per time interval caused by said first thread context, an occupation of a Multiply Divide Unit per time interval caused by said second thread context, a type of instructions executed on said first thread context, a type of instructions executed on said second thread context, an occupation of an arithmetic logic unit per time interval said first context causes and an occupation of an arithmetic logic unit per time interval said second context causes.

20. A method, comprising:

running a thread on a first processing entity,

running a thread on a second processing entity essentially simultaneously to running said first thread,

detecting the use of shared resources by said first processing entity and said second processing entity, and

assigning time for execution of said first thread and said second thread based on said detecting.

21. The method of claim 20,

further comprising detecting an improper execution of instructions in one thread selected from the group consisting of said first thread and said second thread caused by use of shared resources by the respective other one of said first thread and said second thread.

22. The method of claim 20,

further comprising executing a software code to evaluate the result of said detecting.

23. The method of claim 22,

wherein said software code is executed periodically.

24. The method of claim 22,

wherein said software code is executed using a third processing entity.

25. The method of claim 22,

wherein execution of said software code is initiated by a predetermined event.