SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

• US 20110095337A1
• Filed: 10/21/2010
• Published: 04/28/2011
• Est. Priority Date: 10/22/2009
• Status: Active Grant

• Current Assignee: Sanken Electric Company Limited
• Original Assignee: Sanken Electric Company Limited
• Inventors: SATO, Ken
• Granted Patent: US 8,193,561 B2
• Time in Patent Office: Days
• US Class Current: 257/194
• CPC Class Codes: H01L 29/0891 of field-effect transistors with Schottky gate
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/7787 with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET

Abstract

A semiconductor device reduces the on-resistance and, at the same time, raises the breakdown voltage. The drain electrode 20 of the semiconductor device runs through cap layer 13 and electron supply layer 12 and gets to a position lower than two-dimensional electron gas layer 14 in channel layer 11. Thus, the drain electrode 20 directly contacts the channel layer 11, the electron supply layer 12 and the cap layer 13. Angles (acute angles) θ, ø and ψ are formed by the drain electrode 20 and the channel layer 11, the electron supply layer 12 and the cap layer 13 as viewed in the direction in which a hetero interface is formed (the transverse direction in FIG. 1) and relationships of ø<θ and ø≦ψ are established. In other words, ø is made smallest among the angles and the drain electrode 20 is remarkably tapered particularly at the position of the electron supply layer 12.

Claims

1. A semiconductor device comprising:

a hetero structure formed by laying a first semiconductor layer within which a flow path of carriers is formed and a second semiconductor layer made of a material different from that of the first semiconductor layer and laid on the first semiconductor layer; and

an electrode penetrating through the second semiconductor layer, held in contact with the flow path of carriers and tapered so as to make the cross-sectional area parallel to the hetero interface of the hetero structure larger at the side of the second semiconductor layer than at the side of the first semiconductor layer,

the device showing relationships of 0°

<

ø

≦

60° and

ø

≠

ø

,

where θ

is the acute angle formed by the tangent plane of the lateral surface of the electrode and the hetero interface at a position where the electrode contacts the flow path of charge carriers and 0 is the acute angle formed by the tangent plane of the lateral surface of the electrode and the hetero interface at a position where the electrode contacts the second semiconductor layer above the position where the electrode contacts the flow path of charge carriers on respective cross sections taken along the flow direction of charge carriers.

2. The semiconductor device according to claim 1, wherein

a cap layer made of a material with different composition or different element from the second semiconductor layer is formed on the second semiconductor layer and the electrode penetrates through the cap layer,

the device showing a relationship of ø

<

ψ

, where ψ

is the acute angle formed by the tangent plane of the lateral surface of the electrode and the hetero interface at a position where the electrode contacts the cap layer above the position where the electrode contacts the flow path of carriers on a cross section taken along the flow direction of carriers.

3. The semiconductor device according to claim 2, wherein

a step is formed at the lateral surface of the electrode where the electrode contacts the cap layer and the second semiconductor layer so as to make the cross-sectional area of the electrode taken along the hetero interface greater at the side of the cap layer than at the side of the second semiconductor layer as viewed from the interface of the cap layer and the second semiconductor layer.

4. The semiconductor device according to claim 1, wherein

the first and second semiconductor layers respectively have compositions expressed by chemical formulas of Al_xM_yGa_l-x-yN (where 0≦

x<

l, 0≦

y<

l, 0≦

x+y<

l and M contains at least In or B).

5. The semiconductor device according to claim 1, wherein

the flow path of carriers is formed two-dimensionally by carrier gas generated in the first semiconductor layer.

6. The semiconductor device according to claim 1, comprising two electrodes so as to make carriers flow between the two electrodes and a gate electrode arranged on the flow path of carriers.

7. The semiconductor device according to claim 1, further comprising another electrode that penetrates through the second semiconductor layer, contacts the flow path of carriers, and the flow path is made between the another electrode and the electrode, and a gate electrode formed on the flow path of carriers,

the device showing a relationship of ø

′

>

ø

, where ø

′

is the angle formed by the tangent plane of the lateral surface of the another electrode and the hetero interface at a position where the another electrode contacts the second semiconductor layer.

8. The semiconductor device according to claim 1, showing

a relationship of ø

<

θ

.

9. The semiconductor device according to claim 1, showing

a relationship of ø

>

θ

.

10. A method of manufacturing a semiconductor device as defined in claim 1, comprising:

an etching step of forming a recess structure corresponding to the shape of the electrode by locally dry etching the second semiconductor layer and also the first semiconductor layer at least down to the flow path of carriers; and

an electrode forming step of filling an electrode material in the recess structure.