Printed Material Constrained By Well Structures And Devices Including Same

• US 20110095342A1
• Filed: 10/23/2009
• Published: 04/28/2011
• Est. Priority Date: 10/23/2009
• Status: Active Grant

• Current Assignee: Xerox Corporation (Xerox Holdings Corp.)
• Original Assignee: Palo Alto Research Center, Inc. (Xerox Holdings Corp.)
• Inventors: Arias, Ana Claudia, Daniel, Jurgen H.
• Granted Patent: US 8,211,782 B2
• Time in Patent Office: Days
• US Class Current: 257/288
• CPC Class Codes: H01L 21/02288 printing, e.g. ink-jet printing per se B41J
• CPC Class Codes: H01L 21/02488 Insulating materials
• CPC Class Codes: H01L 21/02521 Materials
• CPC Class Codes: H01L 21/02623 Liquid deposition
• CPC Class Codes: H01L 21/02628 using solutions
• CPC Class Codes: H01L 21/38 Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions
• CPC Class Codes: H01L 27/1292 using liquid deposition, e.g. printing
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/78684 having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys H01L29/7869 takes precedence
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H10K 71/13 using printing techniques, e.g. ink-jet printing or screen printing

Abstract

A first patterned contact layer, for example a gate electrode, is formed over an insulative substrate. Insulating and functional layers are formed at least over the first patterned contact layer. A second patterned contact layer, for example source/drain electrodes, is formed over the functional layer. Insulative material is then selectively deposited over at least a portion of the second patterned contact layer to form first and second wall structures such that at least a portion of the second patterned contact layer is exposed, the first and second wall structures defining a well therebetween. Electrically conductive or semiconductive material is deposited within the well, for example by jet-printing, such that the first and second wall structures confine the conductive or semiconductive material and prevent spreading and electrical shorting to adjacent devices. The conductive or semiconductive material is in electrical contact with the exposed portion of the second patterned contact layer to form, e.g., an operative transistor.

Claims

1. A method of forming an active electronic device comprising:

depositing a functional layer over a substrate;

selectively depositing a first patterned contact layer over said functional layer, said first patterned contact layer defining first and second electrodes of said active device;

selectively additively depositing insulating material over at least a portion of said first patterned contact layer to form first and second wall structures such that at least a portion of said patterned contact layer over said first electrode and at least a portion of said patterned contact layer over said second electrode are exposed, said first and second wall structures defining a well region therebetween, and said exposed portions of said patterned contact layer over said first and second electrodes are within said well region; and

selectively depositing a semiconductor layer from a solution within said well region such that said first and second wall structures confine said semiconductor layer therein, and said semiconductor layer within said well region is in physical and electrical contact with said exposed portion of said patterned contact layer over said first and second electrodes.

2. The method of claim 1, wherein said functional layer is a hydrophobic coating.

3. The method of claim 2, wherein said hydrophobic coating is selected from the group consisting of:

hydrophobic silane, nonpolar polymer, silazane, polysilsesquioxane, and fluorocarbon.

4. The method of claim 1, wherein said functional layer is hydrophilic.

5. The method of claim 4, wherein said hydrophilic coating is selected from the group consisting of:

hydrophilic silane, polar polymer, polyethylene glycol, polyethylene oxide, and proteins.

6. The method of claim 1, wherein said first and second wall structures are each formed of at least one droplet deposited by a digital lithography process.

7. The method of claim 1, wherein said first and second wall structures are formed by a laser transfer process.

8. The method of claim 1, wherein said first electrode is a source electrode, said second electrode is a drain electrode, said active device is a transistor, and further comprising, prior to forming said functional layer:

forming a gate electrode over said substrate; and

forming a gate dielectric layer over at least said gate electrode.

9. The method of claim 8, further comprising the step of selectively depositing a passivation material from a solution over said semiconductor layer and between said first and second wall structures such that said first and second wall structures confine said passivation material such that it is substantially limited to a region over said semiconductor layer.

10. The method of claim 1, wherein said first electrode is a source electrode, said second electrode is a drain electrode, said active device is a transistor, and further comprising:

forming a gate dielectric layer over at least said semiconductor layer within said well region from solution; and

forming a gate electrode over said gate dielectric layer; and

whereby the width of said gate electrode is no greater than the lateral width of said well.

11. The method of claim 8, further comprising:

forming a gate dielectric layer over at least said semiconductor layer within said well region; and

forming a gate electrode over said gate dielectric layer; and

whereby the width of said gate electrode is no greater than the lateral width of said well, thereby forming a dual gate device.

12. A method of forming an active electronic device comprising:

selectively depositing a first patterned contact layer over a substrate, said first patterned contact layer defining a first electrode of said active device;

depositing a first insulating layer over said first patterned contact layer so as to cover at least said first electrode;

selectively depositing a second patterned contact layer over said first insulating layer, said second patterned contact layer defining second and third electrodes of said active device, at least a portion of each of said second and third electrodes positioned to overlap portions of said first electrode;

depositing a functional layer over said second patterned contact layer;

selectively additively depositing insulating material over at least a portion of said functional layer to form first and second wall structures, said first wall structure positioned to be substantially over said second electrode, said second wall structure positioned to be substantially over said third electrode, and said first and second wall structures substantially not being over said first electrode except over the regions in which said second and third electrodes overlap said first electrode, said first and second wall structures defining a well region therebetween; and

selectively depositing a semiconductor layer from a solution within said well region such that said first and second wall structures confine said semiconductor layer therein.

13. The method of claim 12, wherein said functional layer is a hydrophobic coating.

14. The method of claim 13, wherein said hydrophobic coating is selected from the group consisting of:

hydrophobic silane, nonpolar polymer, silazane, polysilsesquioxane, and fluorocarbon.

15. The method of claim 12, wherein said functional layer is hydrophilic.

16. The method of claim 15, wherein said hydrophilic coating is selected from the group consisting of:

hydrophilic silane, polar polymer, polyethylene glycol, polyethylene oxide, and proteins.

17. A transistor device, comprising:

a substrate;

a gate electrode formed over said substrate;

a gate dielectric layer formed over said gate electrode and at least a portion of said substrate;

source and drain electrodes formed over said gate electrode such that said source and drain electrodes are spaced apart from said gate electrode in a plane of said gate dielectric layer and further such that a portion of each of said source and drain electrodes overlap a portion of said gate electrode;

a first insulative wall structure formed over at least a portion of said source electrode such that a region of said source electrode is not covered by said first insulative wall structure and a second insulative wall structure formed over at least a region of said drain electrode such that a portion of said drain electrode is not covered by said second insulative wall structure;

a semiconductor layer formed over said functional layer and in physical and electrical contact with said exposed regions of said source and drain electrodes, said semiconductor layer laterally confined by the first and second insulative wall structures; and

a functional layer formed in a layer between said gate dielectric and said first and second insulative wall structures, said functional layer selected from the group consisting of;

a hydrophobic layer and a hydrophilic layer.

18. The transistor device of claim 17, wherein said function layer is formed over said gate dielectric layer and below said source and drain electrodes.

19. The transistor device of claim 17, wherein said functional layer is a hydrophobic layer, and is selected from the group consisting of:

hydrophobic silane, nonpolar polymer, silazane, polysilsesquioxane, and fluorocarbon.

20. The transistor device of claim 17, wherein said functional layer is a hydrophilic layer, and is selected from the group consisting of:

hydrophilic silane, polar polymer, polyethylene glycol, polyethylene oxide, and proteins.