Inductors and Methods for Integrated Circuits

• US 20110095395A1
• Filed: 10/23/2009
• Published: 04/28/2011
• Est. Priority Date: 10/23/2009
• Status: Active Grant

• Current Assignee: Maxim Integrated Products, Inc. (Analog Devices, Inc.)
• Original Assignee: Maxim Integrated Products, Inc. (Analog Devices, Inc.)
• Inventors: Tran, Khanh, Ellul, Joseph P., Godshalk, Edward Martin, Bergemont, Albert
• Granted Patent: US 8,344,478 B2
• Time in Patent Office: Days
• US Class Current: 257/531
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 28/10 Inductors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]

Abstract

Inductors and methods for integrated circuits that result in inductors of a size compatible with integrated circuits, allowing the fabrication of inductors, with or without additional circuitry on a first wafer and the bonding of that wafer to a second wafer without wasting of wafer area. The inductors in the first wafer are comprised of coils formed by conductors at each surface of the first wafer coupled to conductors in holes passing through the first wafer. Various embodiments are disclosed.

Claims

1. An integrated inductor comprising:

a first substrate having a plurality of holes through the first substrate, the holes being filled with an electrically conductive material so as to be accessible from a first surface of the first substrate;

the electrically conductive material in pairs of holes being electrically interconnected at a second surface of the first substrate;

a second substrate having a plurality of electrically conductive areas exposed on a first surface thereof;

the electrically conductive areas on the first surface of the second substrate being electrically connected to the electrically conductive material accessible from a first surface of the first substrate;

the electrically conductive material accessible from a first surface of the first substrate being interconnected to form a multiple turn inductor coil.

2. The integrated inductor of claim 1 wherein the electrically conductive areas on the first surface of the second substrate form the interconnections to form the multiple turn inductor coil.

3. The integrated inductor of claim 1 wherein the second substrate is a semiconductor substrate having an integrated circuit thereon coupled to the inductor coil.

4. The integrated inductor of claim 3 wherein some of the electrically conductive material filling holes in the first substrate are interconnected with the integrated circuit and not the coil, whereby integrated circuit connections on the second substrate are accessible from the second surface of the first substrate.

5. The integrated inductor of claim 3 wherein the first substrate is an oxide.

6. The integrated inductor of claim 1 wherein the first substrate is a semiconductor substrate.

7. The integrated inductor of claim 6 wherein the electrically conductive material filling the holes, the electrical interconnection at a second surface of the first substrate and the interconnection to form a multiple turn inductor are electrically insulated from the first substrate.

8. The integrated inductor of claim 6 wherein the first substrate includes an integrated circuit thereon.

9. The integrated inductor of claim 1 wherein the electrically conductive material filling the holes, the electrical interconnection at a second surface of the first substrate and the interconnection to form a multiple turn inductor are copper.

10. A method of forming an integrated inductor comprising:

providing a first substrate;

etching a pattern of holes part way through the substrate from a first surface of the first substrate;

filling the holes with an conductive material;

depositing and patterning a first conductive layer on the first surface of the first substrate to electrically connect the conductor in pairs of holes;

temporarily gluing a carrier to the first surface of the first substrate;

thinning the first substrate from a second surface opposite the first surface to expose ends of the conductor filling the holes;

electrically connecting a patterned second conductive layer to the exposed ends of the conductive material filling at least some of the holes to electrically connect the patterned second conductive layer, the conductive material filling the at least some of the holes and the first conductive layer to form an electrically conductive coil.

11. The method of claim 10 wherein filling the holes with an conductive material comprises plating the first surface of the substrate to fill the holes and then chemical-mechanical polishing the first surface of the substrate to remove the plating between holes.

12. The method of claim 10 wherein thinning the first substrate from a second surface opposite the first surface to expose ends of the conductor filling the holes comprises coarse grinding, chemical-mechanical polishing and etching.

13. The method of claim 10 wherein providing a first substrate comprises providing a first semiconductor substrate.

14. The method of claim 13 wherein the holes have an oxide layer therein to electrically insulate the first substrate from the conductive material.

15. The method of claim 14 wherein the second substrate includes an integrated circuit thereon.

16. The method of claim 15 wherein at least some of the electrically conductive material filling holes in the first substrate are interconnected with the integrated circuit on the second substrate and not the coil, whereby integrated circuit connections to the integrated circuit on the second substrate are accessible from the first surface of the first substrate.

17. The method of claim 16 wherein the first substrate includes an integrated circuit on the first surface of the first substrate.

18. The method of claim 10 wherein providing a first substrate comprises providing a semiconductor with a thick oxide on the first surface thereof, and thinning the first substrate from a second surface opposite the first surface to expose ends of the conductor filling the holes comprises removing the semiconductor so that the first substrate becomes only an oxide.

19. The method of claim 10 wherein the first and second patterned conductive layers and the conductive material filling the holes are copper.

20. The method of claim 19 wherein the second patterned conductive layer is on a second substrate, and electrically connecting a patterned second conductive layer to the exposed ends of the conductive material filling the holes to electrically connect the patterned second conductive layer, the conductive material filling the holes and the first conductive layer to form an electrically conductive coil comprises thermo-compression bonding the second patterned conductive layer to the exposed ends of the conductive material filling the holes.