Wirebond-less Semiconductor Package

• US 20110095411A1
• Filed: 12/13/2010
• Published: 04/28/2011
• Est. Priority Date: 08/14/2006
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: LOPEZ, Osvaldo J., HERBSOMMER, Juan Alejandro, PRZYBYLEK, George J.
• Granted Patent: US 8,304,903 B2
• Time in Patent Office: Days
• US Class Current: 257/676
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/37011 comprising apertures or cavities
• CPC Class Codes: H01L 2224/37147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/38 of a plurality of strap connectors
• CPC Class Codes: H01L 2224/40095 Kinked
• CPC Class Codes: H01L 2224/40245 the item being metallic
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73221 Strap and wire connectors
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/83801 Soldering or alloying
• CPC Class Codes: H01L 2224/84801 Soldering or alloying
• CPC Class Codes: H01L 23/49524 the additional leads being a tape carrier or flat leads
• CPC Class Codes: H01L 23/49562 for devices being provided for in H01L29/00
• CPC Class Codes: H01L 24/37 of an individual strap connector
• CPC Class Codes: H01L 24/38 of a plurality of strap connectors
• CPC Class Codes: H01L 24/40 of an individual strap connector
• CPC Class Codes: H01L 24/41 of a plurality of strap connectors
• CPC Class Codes: H01L 24/84 using a strap connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/0103 : Zinc [Zn]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01072 : Hafnium [Hf]
• CPC Class Codes: H01L 2924/01076 : Osmium [Os]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/18301 : being an anchoring portion, i.e. mechanical interlocking between the encapsulation resin and another package part
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3011 : Impedance

Abstract

A wirebond-less packaged semiconductor device includes a plurality of I/O contacts, at least one semiconductor die, the semiconductor die having a bottom major surface and a top major surface, the top major surface having at least two electrically isolated electrodes, and a conductive clip system disposed over the top major surface, the clip system comprising at least two electrically isolated sections coupling the electrodes to respective I/O contacts.

Claims

1. A semiconductor device package, comprising

a top surface and a bottom surface parallel to the top surface and four side surfaces perpendicular to the top surface and the bottom surface;

a leadframe having a flat top side, contacts extending from an etched bottom side parallel to the top side, and edges with severed stubs,

the contacts downwardly extending and coplanar with of the bottom surface of the package;

the severed stubs of the leadframe extending outwardly and having ends coextensive with the side surfaces of the package;

a semiconductor chip having a top side affixed to the flat top side of the leadframe with a conductive adhesive;

a clip having a flat top side, a flat bottom side, edges with severed stubs and a downwardly depending leg portion;

the bottom side of the clip affixed to a top side of the semiconductor chip with a conductive adhesive;

the severed stubs of the clip extending outwardly and having ends coextensive with the side surfaces;

the leg portion of the clip affixed to the flat top side of the leadframe; and

the encapsulating material encapsulating the leadframe, the semiconductor chip, the metallic clip, forming the top surface, the bottom surface, and the four side surfaces of the device package, exposing the contacts from the bottom surface and the ends of the stubs at the side surfaces of the package.

2. The semiconductor device package of claim 1, in which the clip has two separate portions each affixed to an electrode on a semiconductor chip surface.

3. The semiconductor device package of claim 1, in which the leadframe has two separate portions each affixed to an electrode on a semiconductor chip surface.

4. The semiconductor device package of claim 2, in which the two separate portions of the clip have similar areas.

5. The semiconductor device package of claim 2, in which each of the two separate portions has a downwardly depending leg portion affixed to the flat top side of the leadframe.

6. The semiconductor device package of claim 5, in which the two downwardly depending leg portions are at two opposite edges of the clip.

7. The semiconductor device package of claim 1, in which the top side of the clip is exposed from the encapsulating material.