MICROELECTRONIC ASSEMBLIES HAVING COMPLIANT LAYERS

• US 20110095441A1
• Filed: 12/21/2010
• Published: 04/28/2011
• Est. Priority Date: 10/31/1995
• Status: Active Grant

• Current Assignee: Tessera, Inc. (Adeia Inc.)
• Original Assignee: Tessera, Inc. (Adeia Inc.)
• Inventors: Karavakis, Konstantine, Fjelstad, Joseph
• Granted Patent: US 8,338,925 B2
• Time in Patent Office: Days
• US Class Current: 257/782
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/02311 Additive methods
• CPC Class Codes: H01L 2224/02313 Subtractive methods
• CPC Class Codes: H01L 2224/0236 Shape of the insulating layers therebetween
• CPC Class Codes: H01L 2224/024 Material of the insulating layers therebetween
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/11334 using preformed bumps
• CPC Class Codes: H01L 2224/114 by blanket deposition of the material of the bump connector
• CPC Class Codes: H01L 2224/116 by patterning a pre-deposited material treatment of parts prior to assembly of the devices H01L21/48
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/1319 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/24011 Deposited, e.g. MCM-D type
• CPC Class Codes: H01L 2224/24226 the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
• CPC Class Codes: H01L 2224/24227 the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
• CPC Class Codes: H01L 2224/274 by blanket deposition of the material of the layer connector
• CPC Class Codes: H01L 2224/45124 : Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/45144 : Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/45147 : Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/45155 : Nickel (Ni) as principal constituent
• CPC Class Codes: H01L 2224/48624 : Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/48724 : Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/48824 : Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/85424 : Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 23/3114 : the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/3121 : a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/4951 : Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
• CPC Class Codes: H01L 23/498 : Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers shape of the substrate H01L23/13
• CPC Class Codes: H01L 23/525 : with adaptable interconnections
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/72 : Detachable connecting means consisting of mechanical auxiliary parts connecting the device, e.g. pressure contacts using springs or clips
• CPC Class Codes: H01L 24/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00011 : Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01009 : Fluorine [F]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01039 : Yttrium [Y]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/01327 : Intermediate phases, i.e. intermetallics compounds
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/1517 : Multilayer substrate
• CPC Class Codes: H01L 2924/351 : Thermal stress

Abstract

A compliant semiconductor chip package assembly includes a semiconductor chip having a plurality of chip contacts, and a compliant layer having a top surface, a bottom surface and sloping peripheral edges, whereby the bottom surface of the compliant layer overlies a surface of the semiconductor chip. The assembly also includes a plurality of electrically conductive traces connected to the chip contacts of the semiconductor chip, the traces extending along the sloping edges to the top surface of the compliant layer. The assembly may include conductive terminals overlying the semiconductor chip, with the compliant layer supporting the conductive terminals over the semiconductor chip. The conductive traces have first ends electrically connected with the contacts of the semiconductor chip and second ends electrically connected with the conductive terminals. The conductive terminals are movable relative to the semiconductor chip.

Claims

1. A microelectronic assembly, comprising:

a semiconductor chip having a first surface extending in lateral directions, at least one edge surface extending in a direction transverse to said lateral directions, and a plurality of contacts exposed at said first surface;

a supporting element adjacent said at least one edge surface and extending in at least one of said lateral directions away from said semiconductor chip, said supporting element having a top surface;

a compliant layer overlying said top surface of said supporting element and said semiconductor chip, said compliant layer having a top surface facing away from said top surface of said supporting element and said first surface of said semiconductor chip, said compliant layer having at least one sloping surface extending between said top surface of said compliant layer and said first surface of said semiconductor chip;

conductive terminals exposed at said top surface of said compliant layer, at least one of said terminals not overlying said first surface of said semiconductor chip;

bond ribbons overlying said top surface of said compliant layer and extending along said at least one sloping surface of said compliant layer, said bond ribbons electrically connecting said chip contacts and said conductive terminals.

2. A microelectronic assembly as claimed in claim 1, wherein said bond ribbons are formed integrally with said terminals.

3. A microelectronic assembly as claimed in claim 1, wherein said bond ribbons and said bond ribbons are formed integrally with said terminals by steps including at least one of plating or depositing a metal over said top surface of compliant layer and over said first surface of said chip.

4. A microelectronic assembly as claimed in claim 3, wherein at least one of said bond ribbons extends from said at least one chip contact to at least one of said terminals.

5. A microelectronic assembly as claimed in claim 1, wherein at least one of said bond ribbons extends from at least one of said chip contacts to at least one of said terminals.

6. A microelectronic assembly as claimed in claim 1, wherein at least one of said bond ribbons extends from at least one of said chip contacts to said at least one terminal which does not overlie said top surface of said semiconductor chip.

7. The microelectronic assembly as claimed in claim 1, wherein a gap is present between said supporting element and said at least one edge surface of said semiconductor chip, and wherein a portion of said compliant layer is disposed in said gap.

8. The microelectronic assembly as claimed in claim 1, further comprising a dielectric layer overlying said bond ribbons, wherein said conductive terminals are accessible through openings in said dielectric layer.

9. The microelectronic assembly as claimed in claim 1, wherein said supporting element is an element selected from the group consisting of a bar, a ring and a heat sink.

10. The microelectronic assembly as claimed in claim 1, wherein said at least one sloping surface of said compliant layer has a first transition region near said top surface of said compliant layer and a second transition region near said first surface of said semiconductor chip, and wherein said first and second transition regions have radii of curvature for facilitating formation of gently curved bond ribbons for increasing the reliability of said bond ribbons and said assembly.

11. The microelectronic assembly as claimed in claim 1, further comprising a passivation layer overlying said first surface of said semiconductor chip, said chip contacts exposed at a surface of said passivation layer and said bond ribbons overlying at least portions of said passivation layer.

12. The microelectronic assembly as claimed in claim 1, further comprising an encapsulant layer overlying said bond ribbons.

13. The microelectronic assembly as claimed in claim 1, wherein said encapsulant layer includes a material selected from the group consisting of a curable liquid, silicone, flexibilized epoxy, thermoplastic and a gel.

14. The microelectronic assembly as claimed in claim 1, wherein said compliant layer consists essentially of a material selected from the group consisting of silicone, flexibilized epoxy, thermosetting epoxy, fluoropolymer, thermoplastic polymer and polyimide.

15. The microelectronic assembly as claimed in claim 1, further comprising a first dielectric layer overlying said first surface of said semiconductor chip, said first dielectric layer having a plurality of apertures in substantial alignment with said contacts for providing access to said contacts, wherein said compliant layer overlies said first dielectric layer.

16. A microelectronic assembly, comprising:

a semiconductor chip having a first surface extending in lateral directions, at least one edge surface extending in a direction transverse to said lateral directions, and a plurality of contacts exposed at said first surface;

a supporting element adjacent said at least one edge surface and extending in at least one of said lateral directions away from said semiconductor chip, said supporting element having a top surface;

a compliant layer overlying said top surface of said supporting element and said semiconductor chip, said compliant layer having a top surface facing away from said top surface of said supporting element and said first surface of said semiconductor chip, said compliant layer having at least one sloping surface extending between said top surface of said compliant layer and said first surface of said semiconductor chip;

conductive terminals exposed at said top surface of said compliant layer, at least one of said terminals not overlying said first surface of said semiconductor chip;

bond ribbons formed integrally with said terminals, said bond ribbons extending along said at least one sloping surface of said compliant layer, said bond ribbons electrically connecting said chip contacts and said conductive terminals.

17. A microelectronic assembly as claimed in claim 16, wherein said bond ribbons are formed integrally with said terminals by steps including at least one of plating or depositing a metal onto said compliant layer and onto said chip.

18. A microelectronic assembly as claimed in claim 17, wherein at least one of said bond ribbons extends from said at least one chip contact to at least one of said terminals.

19. A microelectronic assembly as claimed in claim 16, wherein at least one of said bond ribbons extends from at least one of said chip contacts to at least one of said terminals.

20. A microelectronic assembly as claimed in claim 16, wherein at least one of said bond ribbons extends from at least one of said chip contacts to said at least one terminal which does not overlie said top surface of said semiconductor chip.