Galvanic Isolators and Coil Transducers

• US 20110095620A1
• Filed: 01/04/2011
• Published: 04/28/2011
• Est. Priority Date: 08/28/2006
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Avago Technologies ECBU IP Singapore Pte Limited (Broadcom, Inc.)
• Inventors: Baumgartner, Richard, Ng, Gek-Yong, Trott, Gary R., Fouquet, Julie E.
• Granted Patent: US 8,436,709 B2
• Time in Patent Office: Days
• US Class Current: 307/104
• CPC Class Codes: H01F 17/0006 Printed inductances printed coils for dynamo-electric machines H02K3/26; printed circuits H05K
• CPC Class Codes: H01F 17/0013 with stacked layers
• CPC Class Codes: H01F 19/08 Transformers having magnetic bias, e.g. for handling pulses
• CPC Class Codes: H01F 2019/085 Transformer for galvanic isolation
• CPC Class Codes: H01F 27/2804 Printed windings
• CPC Class Codes: H01F 27/40 Structural association with built-in electric component, e.g. fuse
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48195 the item being a discrete passive component
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H01L 2924/30111 matching
• CPC Class Codes: H03F 2203/45008 the addition of two signals being made by a resistor addition circuit for producing the common mode signal
• CPC Class Codes: H03F 2203/45101 Control of the DC level being present
• CPC Class Codes: H03F 2203/45586 the IC comprising offset generating means
• CPC Class Codes: H03F 3/45192 Folded cascode stages
• CPC Class Codes: H03F 3/45475 using IC blocks as the active amplifying circuit
• CPC Class Codes: H03H 7/52 One-way transmission networks, i.e. unilines
• CPC Class Codes: H04L 25/0266 Arrangements for providing Galvanic isolation, e.g. by means of magnetic or capacitive coupling
• CPC Class Codes: Y10T 29/4902 : Electromagnet, transformer or inductor

Abstract

Disclosed herein are various embodiments of coil transducers and galvanic isolators configured to provide high voltage isolation and high voltage breakdown performance characteristics in small packages. A coil transducer is provided across which data or power signals may be transmitted and received by primary and secondary coils disposed on opposing sides thereof without high voltage breakdowns occurring therebetween. At least portions of the coil transducer are formed of an electrically insulating, non-metallic, non-semiconductor, low dielectric loss material. Circuits are disclosed herein that permit high speed data signals to be transmitted through the coil transducer and faithfully and accurately reconstructed on the opposing side thereof. The coil transducer may be formed in a small package using, by way of example, printed circuit board, CMOS and other fabrication and packaging processes.

Claims

1. (canceled)

9. The coil transducer of claim 1, further comprising an input lead frame and an output lead frame connected to the coil transducer such that the input lead frame is mechanically connected to an upper side of the coil transducer and the output lead frame is mechanically connected to a bottom side of the coil transducer, the bottom side opposing the top side.

10. The coil transducer of claim 1, further comprising an input lead frame and an output lead frame connected to the coil transducer such that the input and output lead frames are both mechanically connected to one of an upper side of the coil transducer and a bottom side of the coil transducer.

2. (canceled)

3. (canceled)

4. (canceled)

5. (canceled)

6. (canceled)

7. (canceled)

8. A coil transducer, comprising:

a generally planar electrically insulating substrate comprising opposing upper and lower surfaces, the substrate comprising an electrically insulating, non-metallic, non-semiconductor low dielectric loss material having a dielectric loss tangent at room temperature that is less than or equal to 0.05;

a first electrical conductor forming a first coil, the first coil being disposed upon, in or near the upper surface, and

a second electrical conductor forming a second coil, the second coil being disposed upon, in or near the lower surface;

at least one of an input lead frame and an output lead frame connected to the coil transducer such that electrically conductive portions of the input and output lead frames do not extend beneath the coil transducer to locations directly beneath the first or second coils;

wherein the first coil is separated from the second coil by at least portions of the substrate, no electrical conductors, vias or terminals are located in portions of the substrate disposed between the first coil and the second coil, the first and second coils are spatially arranged and configured respecting one another such that at least one of power and data signals may be transmitted by the first coil to the second coil across a dielectric barrier comprising the non-semiconductor low dielectric loss material disposed therebetween, the dielectric barrier exceeds about 1 mil in thickness, and a breakdown voltage between the first coil and the second coil exceeds 2,000 volts RMS.

11. (canceled)

12. (canceled)

13. (canceled)

14. (canceled)

15. (canceled)

16. (canceled)

23. The coil transducer of claim 16, further comprising an input lead frame and an output lead frame connected to the coil transducer such that the input lead frame is mechanically connected to an upper side of the coil transducer and the output lead frame is mechanically connected to a bottom side of the coil transducer, the bottom side opposing the top side.

24. The coil transducer of claim 16, further comprising an input lead frame and an output lead frame connected to the coil transducer such that the input and output lead frames are both mechanically connected to one of an upper side of the coil transducer and a bottom side of the coil transducer.

25. The coil transducer of claim 16, further comprising an input lead frame and an output lead frame connected to the coil transducer, and a moldable electrically insulating material encapsulating at least portions of the coil transducer and the input and output lead frames.

17. (canceled)

18. (canceled)

19. (canceled)

20. (canceled)

21. (canceled)

22. A coil transducer, comprising:

a generally planar substrate comprising opposing upper and lower surfaces, the substrate comprising an electrically insulating, non-metallic, non-semiconductor, low dielectric loss material comprising one or more of fiberglass, glass, ceramic, polyimide, polyimide film, a polymer, an organic material, a flex circuit material, epoxy, epoxy resin, a printed circuit board material, PTFE and glass, PTFE and ceramic, PTFE, glass and ceramic, plastic and thermoset plastic;

a first electrical conductor forming a first coil, the first coil being disposed upon, in or near the upper surface, and

a second electrical conductor forming a second coil, the second coil being disposed upon, in or near the lower surface;

at least one of an input lead frame and an output lead frame connected to the coil transducer such that electrically conductive portions of the input and output lead frames do not extend beneath the substrate to locations directly beneath the first or second coils;

wherein the first coil is separated from the second coil by at least portions of the substrate, no electrical conductors, vias or terminals are located in portions of the substrate disposed between the first coil and the second coil, the first and second coils are spatially arranged and configured respecting one, another such that at least one of power and data signals may be transmitted by the first coil to the second coil across a dielectric barrier comprising the non-semiconductor low dielectric loss material disposed therebetween, the dielectric barrier exceeds about 1 mil in thickness, and a breakdown voltage between the first coil and the second coil exceeds 2,000 volts RMS.

26. (canceled)

27. (canceled)

28. (canceled)

29. (canceled)

30. (canceled)

31. A galvanic isolator, comprising:

a generally planar electrically insulating substrate comprising opposing surfaces, the substrate comprising an electrically insulating, non-semiconductor, low dielectric loss material and having a first transmitter coil disposed on the upper surface and a second receiving coil disposed on the lower surface;

a transmitter circuit operably connected to the first transmitter coil and configured to receive an input signal provided to the isolator, and

a receiver circuit operably connected to the second receiving coil;

wherein the transmitter circuit further comprises a pulse generation circuit configured to generate an output pulse at an output thereof corresponding to a transition in the input signal, the first coil is separated from the second coil by at least portions of the substrate, no electrical conductors, vias or terminals are located in portions of the substrate disposed between the first coil and the second coil, the first and second coils are spatially arranged and configured respecting one another such that at least one of power and data signals may be transmitted by the first coil to the second coil across a dielectric barrier comprising the non-semiconductor low dielectric loss material disposed therebetween, the dielectric barrier exceeds about 1 mil in thickness, and a breakdown voltage between the first coil and the second coil exceeds 2,000 volts RMS.

32. The galvanic isolator of claim 31, wherein the output pulse provided by the pulse generation circuit is one of a positive output pulse and a negative output pulse when the transition in the input signal is positive.

33. The galvanic isolator of claim 31, wherein the output pulse provided by the pulse generation circuit is one of a positive output pulse and a negative output pulse when the transition in the input signal is negative.

34. The galvanic isolator of claim 31, wherein the transmitter circuit further comprises a driver circuit operably connected to the output of the pulse generation circuit, the driver circuit comprising at least one drive current source configured to excite the first transmitter coil.

35. The galvanic isolator of claim 31, wherein the drive current source is operably connected to a current mirror circuit such that drive currents provided by the drive current source may be adjusted by the current mirror circuit.

36. A galvanic isolator, comprising:

a generally planar electrically insulating substrate comprising opposing surfaces, the substrate comprising an electrically insulating, non-semiconductor, low dielectric loss material and having a first transmitter coil disposed on the upper surface and a second receiving coil disposed on the lower surface;

a transmitter circuit operably connected to the first transmitter coil and comprising at least one output;

a receiver circuit operably connected to the second receiving coil and comprising at least one input, and

at least one common mode rejection (CMR) circuit operably connected to the output of the transmitter circuit or the input of the receiver circuit, the CMR circuit comprising a two-stage common mode amplifier circuit operably connected to a low impedance matched resistor divider network, the common mode amplifier circuit being configured to drive a center tap of the resistor divider network to a common mode reference voltage of the transmitter output or the receiver input, the common mode amplifier circuit further comprising a first folded cascode structure stage and a second output stage, the output stage comprising a PMOS output device having a first gate drive and an NMOS output device paired therewith and having a second gate drive, the output stage further comprising means for controlling a voltage difference between the first and second gate drives such that the voltage difference controlling means is configured to turn off when a first voltage at the first gate drive is lower than v_p or when a second voltage at the second gate drive is higher than v_n.

37. The galvanic isolator of claim 36, wherein each of the PMOS device and the NMOS device further comprises drains and local feedback capacitors disposed directly between the drains and gates thereof.

38. The galvanic isolator of claim 36, wherein each resistor of the resistor divider network has an impedance less than or equal to 100 ohms.

39. A galvanic isolator, comprising:

a generally planar electrically insulating substrate comprising opposing surfaces, the substrate comprising an electrically insulating, non-semiconductor, low dielectric loss material and having a first transmitter coil disposed on the upper surface and a second receiving coil disposed on the lower surface;

a transmitter circuit operably connected to the first transmitter coil and comprising at least one output;

a receiver circuit operably connected to the second receiving coil and comprising at least one input, and

at least one common mode rejection (CMR) circuit operably connected to the output of the transmitter circuit or the input of the receiver circuit, the CMR circuit comprising a common mode amplifier circuit operably connected to a low impedance matched resistor divider network, the common mode amplifier circuit being configured to drive a center tap of the resistor divider network to a common mode reference voltage of the transmitter output or the receiver input, each resistor in the resistor divider network having an impedance less than or equal to 100 ohms.

40. The galvanic isolator of claim 39, wherein the CMR circuit is further configured to handle transient signals of at least 50 kV/microsecond.

41. The galvanic isolator of claim 39, wherein the common mode amplifier circuit further comprises a first folded cascode structure stage and a second output stage, the output stage comprising a PMOS output device having a first gate drive and an NMOS output device paired therewith and having a second gate drive, the output stage further comprising means for controlling a voltage difference between the first and second gate drives such that the voltage difference controlling means is configured to turn off when a first voltage at the first gate drive is lower than v_p or when a second voltage at the second gate drive is higher than v_n.

42. A galvanic isolator, comprising:

a generally planar electrically insulating substrate comprising opposing surfaces, the substrate comprising an electrically insulating, non-semiconductor, low dielectric loss material and having a first transmitter coil disposed on the upper surface and a second receiving coil disposed on the lower surface;

a transmitter circuit operably connected to the first transmitter coil and comprising at least one output, and

a receiver circuit operably connected to the second receiving coil and comprising at least one input, a fully differential input stage circuit operably connected to the input, a fully differential comparator circuit operably connected to the input stage circuit, and a decoder circuit operably connected to the comparator circuit, the receiver circuit being configured to sense a positive output pulse followed by a negative output pulse when a rising edge of an input signal is provided to an input of the transmitter circuit.

43. The galvanic isolator of claim 42, wherein the receiver circuit is further configured to sense a negative pulse followed by a positive pulse when a falling edge of the input signal is provided to the input of the transmitter circuit.

44. The galvanic isolator of claim 42, wherein the receiver circuit further comprises a DC refresh circuit comprising a watchdog timer circuit configured to monitor transitions in the input signal.

45. The galvanic isolator of claim 42, wherein the watchdog timer circuit is further configured to initiate “

keep-alive”

pulses thereby to maintain an output DC state when no signal transitions have been detected in the input signal by the watchdog timer circuit after a predetermined period of time has passed.

46. A galvanic isolator, comprising:

a generally planar electrically insulating substrate comprising opposing surfaces, the substrate comprising an electrically insulating, non-semiconductor, low dielectric loss material and having a first transmitter coil disposed on the upper surface and a second receiving coil disposed on the lower surface;

a transmitter circuit operably connected to the first transmitter coil and comprising at least one output, and

a receiver circuit operably connected to the second receiving coil and comprising at least one input, a fully differential input stage circuit operably connected to the input, a fully differential comparator circuit operably connected to the input stage circuit, and a decoder circuit operably connected to the comparator circuit, the receiver circuit being configured to sense a negative output pulse followed by a positive output pulse when a rising edge of an input signal is provided to an input of the transmitter circuit.

47. The galvanic isolator of claim 46, wherein the receiver circuit is further configured to sense a positive pulse followed by a negative pulse when a falling edge of the input signal is provided to the transmitter circuit.

48. The galvanic isolator of claim 46, wherein the receiver circuit further comprises a DC refresh circuit comprising a watchdog timer circuit configured to monitor transitions in the input signal.

49. The galvanic isolator of claim 46, wherein the watchdog timer circuit is further configured to initiate “

keep-alive”

pulses thereby to maintain an output DC state when no signal transitions are detected in the input signal by the watchdog timer circuit after a predetermined period of time has passed.

50. The galvanic isolator of claim 46, wherein the CMR circuit is further configured to handle transient signals of at least 50 kV/microsecond.

51. The galvanic isolator of claim 46, wherein the receiver circuit is further configured to detect data pulses sequentially transmitted by the transmitter circuit over a predetermined time window.