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Enhancement of Power Management Using Dynamic Voltage and Frequency Scaling and Digital Phase Lock Loop High Speed Bypass Mode

  • US 20110095794A1
  • Filed: 10/28/2009
  • Published: 04/28/2011
  • Est. Priority Date: 10/28/2009
  • Status: Active Grant
First Claim
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1. An apparatus for clock and voltage scaling on an interface, the apparatus comprising:

  • a device power manager coupled to the interface and arranged to supply a scalable frequency clock to the interface;

    a delay-locked loop supplied by a substantially constant fixed frequency clock from the device manager and a substantially constant voltage from an embedded low dropout regulator, the delay-locked loop arranged to generate a unique code depending on at least one of process, voltage, and temperature; and

    a plurality of controlled delay line elements coupled to the delay-locked loop and arranged to use the unique code to build a delay and generate an appropriate delayed data strobe, the delay being adjusted by having up to N controlled delay line elements chained together, N being a ratio between the substantially constant fixed frequency and the scalable frequency.

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