Enhancement of Power Management Using Dynamic Voltage and Frequency Scaling and Digital Phase Lock Loop High Speed Bypass Mode

• US 20110095794A1
• Filed: 10/28/2009
• Published: 04/28/2011
• Est. Priority Date: 10/28/2009
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Dubost, Gilles, Dubois, Sylvain, Mair, Hugh Thomas, Dahan, Franck
• Granted Patent: US 8,207,764 B2
• Time in Patent Office: Days
• US Class Current: 327/158
• CPC Class Codes: H03L 7/0805 the loop being adapted to provide an additional control signal for use outside the loop
• CPC Class Codes: H03L 7/0812 and where no voltage or current controlled oscillator is used
• CPC Class Codes: H03L 7/22 using more than one loop

Abstract

An apparatus for clock/voltage scaling includes a device power manager arranged to supply a scalable frequency clock to an interface; a delay-locked loop, supplied by a constant fixed frequency clock and a constant voltage, arranged to generate a unique code depending on process, voltage, and/or temperature; and controlled delay line elements coupled to the delay-locked loop, arranged to generate an appropriate delayed data strobe based on the unique code. A method for a digital phase lock loop high speed bypass mode includes providing a first digital phase lock loop in a first high speed clock domain; providing a second digital phase lock loop in a second clock domain; controlling an output of a first glitchless multiplexer according to preselected settings using a device power manager synchronized locally; and controlling an output of a second glitchless multiplexer using a control logic element of the second digital phase lock loop.

Claims

1. An apparatus for clock and voltage scaling on an interface, the apparatus comprising:

a device power manager coupled to the interface and arranged to supply a scalable frequency clock to the interface;

a delay-locked loop supplied by a substantially constant fixed frequency clock from the device manager and a substantially constant voltage from an embedded low dropout regulator, the delay-locked loop arranged to generate a unique code depending on at least one of process, voltage, and temperature; and

a plurality of controlled delay line elements coupled to the delay-locked loop and arranged to use the unique code to build a delay and generate an appropriate delayed data strobe, the delay being adjusted by having up to N controlled delay line elements chained together, N being a ratio between the substantially constant fixed frequency and the scalable frequency.

2. The apparatus of claim 1, wherein the interface includes a memory controller.

3. The apparatus of claim 1 further comprising:

a plurality of the plurality of controlled delay line elements each coupled to the delay-locked loop and each arranged to use the unique code to build the delay and generate an appropriate respective delayed data strobe.

4. The apparatus of claim 1, wherein the interface is arranged to switch between one of the controlled delay line elements and a chain of more than one of the controlled delay line elements based on a handshake protocol with the device power manager when there is no on-going access on a second interface.

5. The apparatus of claim 1, wherein the substantially constant fixed frequency clock and the scalable frequency clock are derived from the same clock source.

6. The apparatus of claim 1, wherein the substantially constant fixed frequency clock and the scalable frequency clock are not balanced.

7. The apparatus of claim 1, wherein the up to N controlled delay line elements are chained together by at least one multiplexer.

8. The apparatus of claim 1, wherein the scalable frequency clock that scales the frequency supplied to the interface may be changed.

9. The apparatus of claim 1, wherein the interface is a double data rate interface.

10. The apparatus of claim 1, wherein the substantially constant fixed frequency clock and the scalable frequency clock are separate.

11. The apparatus of claim 1, wherein the unique code remains substantially stable for at least one of the process, the voltage, and the temperature when the scalable frequency clock scales the frequency.

12. A method for a digital phase lock loop high speed bypass mode, the method comprising:

providing a first digital phase lock loop in a first clock domain having a high speed clock;

providing at least one second digital phase lock loop in a second clock domain, the at least one second digital phase lock loop having a first glitchless multiplexer having the high speed clock as one input and a low speed system reference clock as another input and a second glitchless multiplexer having a first output of the first glitchless multiplexer as a first input and a synthesized clock from a core of the at least one second digital phase lock loop as a second input;

controlling the first output of the first glitchless multiplexer according to preselected settings using a device power manager synchronized locally to ensure proper switching; and

controlling a second output of the second glitchless multiplexer using a control logic element of the at least one second digital phase lock loop, the second output of the second glitchless multiplexer comprising the synthesized clock when the at least one second digital phase lock loop is in a lock mode and comprising the first output of the first glitchless multiplexer when the at least second digital phase lock loop is in the digital phase lock loop high speed bypass mode.

13. The method of claim 12, wherein the first digital phase lock loop supplies the high speed clock to the at least one second digital phase lock loop.

14. The method of claim 12, wherein controlling the first output of the first glitchless multiplexer according to preselected settings using the device power manager synchronized locally further comprises using a synchronization element disposed in the at least one second digital phase lock loop.

15. The method of claim 12, wherein the first output of the first glitchless multiplexer when the at least one second digital phase lock loop is in the digital phase lock loop high speed bypass mode comprises the high speed clock.

16. The method of claim 12, wherein the first output of the first glitchless multiplexer when the at least one second digital phase lock loop is in the digital phase lock loop high speed bypass mode comprises the low speed system reference clock.

17. The method of claim 12, wherein the low speed system reference clock is input to the core of the at least one second digital phase lock loop.

18. The method of claim 12, wherein the control logic element of the at least one second digital phase lock loop is coupled to the core of the at least one second digital phase lock loop.

19. The method of claim 12, wherein the first output of the first glitchless multiplexer when the at least one second digital phase lock loop is in the digital phase lock loop high speed bypass mode comprises the high speed clock.

20. The method of claim 12, wherein the first output of the first glitchless multiplexer when the at least one second digital phase lock loop is in the digital phase lock loop high speed bypass mode comprises the low speed system reference clock.

21. A system for clock and voltage scaling on an interface and for providing a digital phase lock loop high speed bypass mode, the system comprising:

a device power manager coupled to the interface and arranged to supply a scalable frequency clock to the interface; and

a delay-locked loop supplied by a substantially constant fixed frequency clock from the device manager and a substantially constant voltage from an embedded low dropout regulator, the delay-locked loop arranged to generate a unique code depending on at least one of process, voltage, and temperature.

22. The system of claim 21, further comprising:

a plurality of controlled delay line elements coupled to the delay-locked loop and arranged to use the unique code to build a delay and generate an appropriate delayed data strobe, the delay being adjusted by having up to N controlled delay line elements chained together, N being a ratio between the substantially constant fixed frequency and the scalable frequency.

23. The system of claim 22, further comprising:

a first digital phase lock loop in a first clock domain having a high speed clock; and

at least one second digital phase lock loop in a second clock domain, the at least one second digital phase lock loop having a first glitchless multiplexer having the high speed clock as one input and a low speed system reference clock as another input and a second glitchless multiplexer having a first output of the first glitchless multiplexer as a first input and a synthesized clock from a core of the at least one second digital phase lock loop as a second input, wherein the device power manager is arranged to control the first output of the first glitchless multiplexer according to preselected settings and is synchronized locally to ensure proper switching.

24. The system of claim 23, further comprising:

a control logic element of the at least one second digital phase lock loop arranged to control a second output of the second glitchless multiplexer, the second output of the second glitchless multiplexer comprising the synthesized clock when the at least one second digital phase lock loop is in a lock mode and comprising the first output of the first glitchless multiplexer when the at least one second digital phase lock loop is in the digital phase lock loop high speed bypass mode.