BROADCAST RECEIVER SYSTEM

• US 20110096241A1
• Filed: 01/08/2009
• Published: 04/28/2011
• Est. Priority Date: 05/28/2008
• Status: Active Grant

• Current Assignee: Mirics Semiconductor Limited
• Original Assignee: Mirics Semiconductor Limited
• Inventors: Eaton, Anthony, Budin, Dan, Ahluwalia, Keith, Atkinson, Simon
• Granted Patent: US 8,310,601 B2
• Time in Patent Office: Days
• US Class Current: 348/726
• CPC Class Codes: G06F 11/0757 by exceeding a time limit, i.e. time-out, e.g. watchdogs
• CPC Class Codes: H04N 21/414 Specialised client platforms, e.g. receiver in car or embedded in a mobile appliance
• CPC Class Codes: H04N 21/426 Internal components of the client ; Characteristics thereof H04N5/44 takes precedence

Abstract

An interface circuit configured to connect between (a) a broadcast receiver tuner and associated circuitry for the receiving and processing of broadcast radio frequency signals, and (b) a general purpose computer device programmed with software demodulation code configured to engage a general purpose processor in signal demodulation functions, the interface circuit comprising: a data interface comprising a packetisation buffer connected to receive (i) digital signal sample data from a signal path of the tuner and associated circuitry and (ii) indications of control settings which are applied to one or more configurable components during taking of the sample data, said packetisation buffer being operable to construct packets comprising blocks of sample data and header information carrying said control settings indications; a control interface configured to receive control instructions from tuner control code running on the general purpose computer device; and a microcontroller operable to receive the control instructions from the control interface and distribute corresponding control settings to configurable components of the tuner and associated circuitry, said microcontroller also being operable to supply indications of relevant control settings to said packetisation buffer.

Claims

1. An interface circuit configured to connect between (a) a broadcast receiver tuner and associated circuitry for the receiving and processing of broadcast radio frequency signals, and (b) a general purpose computer device programmed with software demodulation code configured to engage a general purpose processor in signal demodulation functions, the interface circuit comprising:

a data interface comprising a packetization buffer connected to receive (i) digital signal sample data from a signal path of the tuner and associated circuitry and (ii) indications of control settings which are applied to one or more configurable components during taking of the sample data, said packetization buffer being operable to construct packets comprising blocks of sample data and header information carrying said control settings indications;

a control interface configured to receive control instructions from tuner control code running on the general purpose computer device; and

a microcontroller operable to receive the control instructions from the control interface and distribute corresponding control settings to configurable components of the tuner and associated circuitry, said microcontroller also being operable to supply indications of relevant control settings to said packetization buffer.

2. An interface circuit according to claim 1, wherein the indications of relevant control settings comprise data sampling rate indications applying in respect of the signal sample data.

3. An interface circuit according to claim 1, wherein the indications of relevant control settings comprise tuner frequency indications applying in respect of the signal sample data.

4. An interface circuit according to claim 1, wherein the indications of relevant control settings comprise tuner gain indications applying in respect of the signal sample data.

5. An interface circuit according to claim 1, further comprising a compression buffer connected between (i) the tuner and associated circuitry and (ii) the packetization buffer.

6. An interface circuit according to claim 5, wherein the microcontroller can disable or enable the compression in dependence upon whether or not the data transfer rate between the interface circuit and the general purpose computer device exceeds a predetermined threshold rate.

7. An interface circuit according to claim 5 or 6, wherein the compression buffer and associated logic implement a bit dropping algorithm.

8. An interface circuit according to claim 1, comprising a standard computer interface deployed between the interface circuit and the general purpose computing device.

9. An interface circuit according to claim 8, wherein said standard computer interface is a USB interface.

10. An interface implemented at least partly in computer code and configured to connect between (a) a demodulator implemented in software on the general purpose computing device and (b) an interface circuit associated with a separate hardware tuner for receiving broadcast signals, said interface comprising:

a data interface for receiving packetized signal sample data including header information comprising control settings indications which are applied during taking of the sample data;

a control interface operable to receive control instructions from tuner control code, setting control inputs of configurable tuner components and further operable to forward said control instructions to a complimentary interface associated with the tuner circuitry;

tuner control code operable to issue control instructions intended to change a control setting of a configurable component of the tuner circuitry;

a log of at least one issued instruction; and

a packet monitoring module operable to detect control settings indications for configurable components of the tuner and to compare them with the log to determine when an instruction issued by the tuner control code has been implemented at the configurable component of the tuner circuitry.

14. An interface circuit according to claims 10 to 13, wherein the tuner control code is configured to issue instructions relating to amplifier again of the tuner and a detected indication comprises a gain value applying in respect of the signal sample data.

16. An interface circuit according to claim 10, wherein the tuner control code is configured to issue instructions applying to an analogue to digital converter associated with the tuner circuit and a detected indication comprises a data sampling rate applying in respect of the signal sample data.

17. An interface circuit according to claims 10, wherein the tuner control code is configured to issue instructions applying to frequency selection of the tuner and a detected indication comprises a tuner frequency applying in respect of the signal sample data.

18. An interface circuit according to claim 16, wherein the tuner control code is configured to issue instructions relating to amplifier again of the tuner and a detected indication comprises a gain value applying in respect of the signal sample data.

19. An interface according to claim 10, wherein said tuner and modulator are capable of handling TV broadcast signals.

11. An interface implemented at least partly in computer code and configured to connect between (a) a demodulator implemented in software on the general purpose computing device and (b) an interface circuit associated with a separate hardware tuner for receiving broadcast signals, said interface comprising:

a data interface for receiving packetized signal sample data including header information comprising control settings indications which applied during taking of the sample data;

a control interface operable to receive control instructions from tuner control code, setting control inputs of configurable tuner components and further operable to forward said control instructions to a complimentary interface associated with the tuner circuitry;

tuner control code operable to issue control instructions intended change a control setting of a configurable component of the tuner circuitry; and

a timer module recording time since instruction issue, operable to determine that an instruction issued by the tuner control code has been implemented at the configurable component of the tuner circuitry a predetermined period after issue.

12. An interface circuit according to claim 11, wherein the tuner control code is configured to issue instructions applying to an analogue to digital converter associated with the tuner circuit and a detected indication comprises a data sampling rate applying in respect of the signal sample data.

13. An interface circuit according to claim 11, wherein the tuner control code is configured to issue instructions applying to frequency selection of the tuner and a detected indication comprises a tuner frequency applying in respect of the signal sample data.

15. An interface according to claim 11, wherein said tuner and modulator are capable of handling TV broadcast signals.