DYNAMIC SENSE CURRENT SUPPLY CIRCUIT AND ASSOCIATED METHOD FOR READING AND CHARACTERIZING A RESISTIVE MEMORY ARRAY

• US 20110096587A1
• Filed: 10/23/2009
• Published: 04/28/2011
• Est. Priority Date: 10/23/2009
• Status: Active Grant

• Current Assignee: Nantero Incorporated
• Original Assignee: Nantero Incorporated
• Inventors: ROSENDALE, Glen, KIM, Young W.
• Granted Patent: US 8,351,239 B2
• Time in Patent Office: Days
• US Class Current: 365/148
• CPC Class Codes: G11C 11/56 using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
• CPC Class Codes: G11C 11/5678 using amorphous/crystalline phase transition storage elements
• CPC Class Codes: G11C 11/5685 using storage elements comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/0002 using resistive RAM [RRAM] elements
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 2013/0045 Read using current through the cell
• CPC Class Codes: G11C 2013/0054 Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell
• CPC Class Codes: G11C 2029/5006 Current
• CPC Class Codes: G11C 2211/5645 Multilevel memory with current-mirror arrangements
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/026 in sense amplifiers
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing
• CPC Class Codes: G11C 7/1045 Read-write mode select circuits
• CPC Class Codes: G11C 7/14 Dummy cell management; Sense reference voltage generators

Abstract

A dynamic sense current supply circuit and an associated method for rapidly characterizing a resistive memory array is disclosed. In one embodiment, the disclosed circuit comprises a first and second dynamically programmable current mirror sub-circuit. Responsive to a bank of control signals, each dynamically programmable current mirror sub-circuit provides a dynamically adjustable current scaling factor. These scaling factors are used to scale a supplied reference current to generate a plurality of sense currents which can be used within a plurality of read operations on a resistive memory array. A digital circuit is also provided to sense and store the result of each read operation.

Claims

1. An electronic circuit for characterizing a resistive memory array, said circuit comprising:

a first current mirror sub-circuit, said first current mirror sub-circuit comprising a first stage and a second stage, said second stage comprising at least two current branches and wherein at least one of said current branches is responsive to an enable control;

a second current mirror sub-circuit, said second current mirror sub-circuit comprising a first stage and a second stage, said second stage comprising at least two current branches and wherein at least one of said current branches is responsive to an enable control;

a reference current terminal to apply an external reference current to said first current mirror sub-circuit to generate a first current through said first current mirror sub-circuit;

an interconnection to couple said first current to said second current mirror sub-circuit;

a sense current terminal to apply a sense current passed through said second current mirror sub-circuit to a memory cell under test; and

a digital circuit element to generate a digital signal indicative of electrical current flowing through said memory cell under test.

2. The circuit of claim 1 wherein at least one of the first and second current mirror sub-circuits are substantially comprised of field effect transistors, each of said field effect transistors having a gate area ratio.

3. The circuit of claim 2, wherein each field effect transistor has the same gate area ratio.

4. The circuit of claim 2, wherein at least one field effect transistor has a different gate area ratio.

5. The circuit of claim 2, wherein each field effect transistor has a different gate area ratio.

6. The circuit of claim 1, wherein said second stage of each of said first current mirror sub-circuit and said second current mirror sub-circuit comprises three current branches.

7. The circuit of claim 2 wherein said gate area ratios within said field effect transistors comprising at least one of said first and second current mirror sub-circuits are selected to provide a desired current scaling factor through at least one of said first and second current mirror sub-circuits.

8. The circuit of claim 1 wherein at least one of said first and second current mirror sub-circuits provides at least one programmable current scaling factor through at least one of said first and second current mirror sub-circuits.

9. The circuit of claim 8 wherein the at least one programmable current scaling factor is responsive to at least one digital enable control signal.

10. The circuit of claim 1 wherein said interconnection is a current mirror circuit.

11. The circuit of claim 1 wherein said digital circuit element is comprised of at least one digital logic gate.

12. The circuit of claim 11 wherein said digital circuit element is comprised of at least one inverter.

13. The circuit of claim 1 further comprising at least one additional current mirror sub-circuit.

14. The circuit of claim 13, wherein said at least one additional current mirror sub-circuit provides at least one additional current scale factor.

15. A method for characterizing a resistive memory array, said memory array comprising a plurality of memory cells, said method comprising:

electrically coupling a dynamic sense current supply circuit to a first memory cell within said memory array;

generating a first sense current through said dynamic sense current supply circuit to perform a read operation;

recording the result of said read operation;

repeating the steps of generating and recording for a predetermined range of sense currents;

electrically coupling to a second memory cell within said memory array and repeating the steps of generating and recording for a predetermined range of sense currents; and

further repeating the steps of electrically coupling, generating, and recording to generate a characterization for each of said plurality of memory cells within said resistive memory array.

16. The method of claim 15 where in said desired plurality of memory cells includes every memory cell within said resistive memory array.