MULTI-PAIR GIGABIT ETHERNET TRANSCEIVER HAVING A SINGLE-STATE DECISION FEEDBACK EQUALIZER
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Abstract
Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitter'"'"'s partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow. A receive clock signal is generated such that it is synchronous in frequency with analog sampling clock signals and has a particular phase offset with respect to one of the sampling clock signals. This phase offset is adjusted such that system performance degradation due to coupling of switching noise from the digital sections to the analog sections is substantially minimized.
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Citations
48 Claims
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1-12. -12. (canceled)
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13. An integrated circuit communication device comprising:
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a slicer for receiving a multi-dimensional signal corresponding to a plurality of paths, wherein the slicer is operable to generate a decision signal corresponding to each of the plurality of paths; a decision feedback equalizer coupled in feedback fashion to the slicer to receive the decision signals from the slicer, wherein the decision feedback equalizer is operable to produce a representation signal corresponding to each of a plurality of paths; and a multi-dimensional processor operable to generate the multi-dimensional signal, wherein the multi-dimensional signal comprises an independent feedback signal for each of the plurality of paths, and wherein at least one independent feedback signal is operably generated according to more than one representation signal. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24)
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25. A method of processing a communication signal, comprising:
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receiving a multi-dimensional signal corresponding to a plurality of paths; generating a decision signal corresponding to each of the plurality of paths; providing the decision signals in feedback fashion to a decision feedback equalizer; producing a representation signal corresponding to each of a plurality of paths based on the decision signals; and generating the multi-dimensional signal, wherein the multi-dimensional signal comprises an independent feedback signal for each of the plurality of paths, and wherein at least one independent feedback signal is operably generated according to more than one representation signal. - View Dependent Claims (26, 27, 28, 29, 30, 31, 32, 33)
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34. A decoder for a multiple-input, multiple-output communication device, comprising:
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a receiver operable to process a multiple-input signal, wherein the receiver receives feedback signals corresponding to X symbol streams, wherein X is greater than one; an estimate generator operable to generate initial decisions for X symbol streams based on the processed multiple-input signal; and a decision feedback generator coupled in feedback fashion to the estimate generator to receive the initial decisions, wherein the decision feedback equalizer is operable to produce a feedback signal corresponding to at least one symbol stream. - View Dependent Claims (35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48)
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Specification