ARRAY SUBSTRATE FOR LIQUID CRYSTAL DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME

• US 20110097857A1
• Filed: 01/04/2011
• Published: 04/28/2011
• Est. Priority Date: 06/30/2006
• Status: Active Grant

• Current Assignee: Dong-Young Kim, Ji Hyun Jung
• Original Assignee: Dong-Young Kim, Ji Hyun Jung
• Inventors: JUNG, Ji Hyun, Kim, Dong-Young
• Granted Patent: US 7,977,175 B2
• Time in Patent Office: Days
• US Class Current: 438/158
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/78633 with a light shield

Abstract

An array substrate for a liquid crystal display device includes a gate line and a data line crossing each other on a substrate to define a pixel region, an insulating layer between the gate line and the data line, a gate electrode extending from the gate line, and a transistor in the pixel region having an active layer on the insulating layer, ohmic contact layers of a first material that are adjacent to ends of the active layer, buffer layers of a second material, which is different from the first material, on the ohmic contact layers, a source electrode contacting one of the buffer layers and a drain electrode contacting another one of the buffer layers, wherein the active layer is in an island shape over the gate electrode and within a boundary defined by a perimeter of the gate electrode.

Claims

1-18. -18. (canceled)

19. A method of fabricating an array substrate for a liquid crystal display device, comprising:

forming a gate electrode on a substrate and a gate line connected to the gate electrode;

forming a first insulating layer on the gate line and gate electrode;

forming an active layer on the first insulating layer;

forming an ohmic contact layer on the active layer;

patterning the active layer and the ohmic contact layer to form an island shape over the gate electrode and within a boundary defined by a perimeter of the gate electrode having an active layer pattern;

forming a transparent conductive material layer and an opaque conductive material layer over the island shape;

patterning the transparent conductive material layer and the opaque conductive material layer to form source and drain electrodes;

patterning the ohmic contact pattern to form ohmic contact layers adjacent to the ends of the active layer under the source and electrodes;

forming a second insulating layer over the substrate; and

patterning the second insulating layer and the opaque conductive material layer of the drain electrode to form the pixel electrode.

20. The method of fabricating an array substrate for a liquid crystal display device according to claim 19, wherein a buffer layer is formed on the ohmic contact layer prior to the patterning the active layer and the ohmic contact layer, and the patterning the active layer and the ohmic contact layer includes patterning the buffer layer as a part of the island shape formed over the gate electrode and within a boundary defined by a perimeter of the gate electrode having an active layer pattern.

21. The method of fabricating an array substrate for a liquid crystal display device according to claim 19, wherein the forming a gate electrode on a substrate and a gate line includes providing a gate pad at one end of the gate line and the forming the transparent conductive material layer and the opaque conductive material layer over the island shape includes providing the transparent conductive material layer and the opaque conductive material layer over the gate pad.

22. A method of fabricating an array substrate for a liquid crystal display device, comprising:

forming a gate electrode, a gate line connected to the gate electrode and a gate pad at one end of the gate line through a first mask process;

forming a first insulating layer, an active layer and an ohmic contact pattern on the gate electrode through a second mask process, the first gate insulating layer exposing the gate pad;

forming source and drain electrodes on the ohmic contact pattern, a pixel pattern connected to the drain electrode, a data line connected to the source electrode, a data pad pattern at one end of the data line and a gate pad terminal pattern contacting the gate pad through a third mask process, the pixel pattern including a first pixel metal layer of a transparent conductive material and a second pixel metal layer of an opaque conductive material, the data pad pattern including a first data pad metal layer of the transparent conductive material and a second data pad metal layer of the opaque conductive material, the gate pad terminal pattern including a first gate pad terminal metal layer of the transparent conductive material and a second gate pad terminal metal layer of the opaque conductive material; and

removing the second pixel pattern metal layer, the second gate pad terminal metal layer and the second data pad metal layer through a fourth mask process to form a pixel electrode of the first pixel pattern metal layer, a gate pad terminal of the first gate pad terminal metal layer and a data pad of the first data pad metal layer.

23. The method according to claim 22, wherein the second mask process comprises forming a buffer metal pattern between the ohmic contact pattern and the source electrode and between the ohmic contact pattern and the drain electrode.

24. The method according to claim 23, wherein the third mask process comprises etching the buffer metal pattern using the source and drain electrodes as an etching mask to form a buffer metal layer exposing the ohmic contact pattern.

25. The method according to claim 22, wherein the second mask process comprises:

sequentially forming the first insulating layer, an intrinsic amorphous silicon layer, an impurity-doped amorphous silicon layer and a first photoresist layer on the gate electrode, the gate line and the gate pad;

exposing the first photoresist layer through a second mask having a transmitting portion, a blocking portion and a half-transmitting portion;

developing the first photoresist layer to form a first photoresist pattern exposing the impurity-doped amorphous silicon layer corresponding to the gate pad, a portion the first photoresist pattern corresponding to the active layer having a first thickness and the other portion of the first photoresist layer having a second thickness smaller than the first thickness;

etching the impurity-doped amorphous silicon layer, the intrinsic amorphous silicon layer and the first insulating layer using the first photoresist pattern as an etching mask to expose the gate pad;

removing the other portion of the first photoresist layer having the second thickness to form a second photoresist pattern corresponding to the active layer; and

etching the impurity-doped amorphous silicon layer and the intrinsic amorphous silicon layer using the second photoresist pattern as an etching mask.

26. The method according to claim 25, wherein the transmitting portion and the blocking portion of the second mask correspond to the gate pad and the active layer, respectively.

27. The method according to claim 22, wherein the third mask process comprises:

sequentially forming a transparent conductive layer, an opaque conductive layer and a second photoresist layer on the ohmic contact pattern;

exposing the second photoresist layer through a third mask;

developing the second photoresist layer to form a third photoresist pattern corresponding to the source and drain electrodes, a fourth photoresist pattern corresponding to the pixel pattern, a fifth photoresist pattern corresponding to the gate pad and a sixth photoresist pattern corresponding to the data pad;

etching the opaque conductive layer and the transparent conductive layer using the third, fourth, fifth and sixth photoresist patterns as an etching mask; and

etching the ohmic contact pattern using the source and drain electrodes as an etching mask to form an ohmic contact layer exposing the active layer.

28. The method according to claim 27, wherein the source electrode includes a first source metal layer of the transparent conductive material and a second source metal layer of the opaque conductive material, the drain electrode includes a first drain metal layer of the transparent conductive material and a second drain metal layer of the opaque conductive material, and the data line includes a first data metal layer of the transparent conductive material and a second data metal layer of the opaque conductive material.

29. The method according to claim 22, wherein the fourth mask process comprises:

sequentially forming a second insulating layer and a third photoresist layer on the source and drain electrodes, the pixel pattern, the gate pad terminal pattern, the data line and the data pad pattern;

exposing the third photoresist layer through a fourth mask;

developing the third photoresist layer to form a seventh photoresist pattern exposing the second insulating layer corresponding to the pixel pattern, the gate pad terminal pattern and the data pad pattern; and

etching the second insulating layer, the second pixel metal layer, the second gate pad terminal metal layer and the second data pad metal layer using the seventh photoresist pattern as an etching mask.

30. The method according to claim 29, wherein the second insulating layer is etched by a dry etching method, and the second pixel metal layer, the second gate pad terminal metal layer and the second data pad metal layer are etched by a wet etching method.