STI Shape Near Fin Bottom of Si Fin in Bulk FinFET

• US 20110097889A1
• Filed: 07/26/2010
• Published: 04/28/2011
• Est. Priority Date: 10/27/2009
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lee, Tsung-Lin, Chen, Hung-Ming, Yuan, Feng, Chang, Chang-Yun
• Granted Patent: US 9,953,885 B2
• Time in Patent Office: Days
• US Class Current: 438/595
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A method of forming an integrated circuit structure includes providing a semiconductor substrate including a top surface; forming a first insulation region and a second insulation region in the semiconductor substrate; and recessing the first insulation region and the second insulation region. Top surfaces of remaining portions of the first insulation region and the second insulation region are flat surfaces or divot surfaces. A portion of the semiconductor substrate between and adjoining removed portions of the first insulation region and the second insulation region forms a fin.

Claims

1. A method of forming an integrated circuit structure, the method comprising:

providing a semiconductor substrate comprising a top surface;

forming a first insulation region and a second insulation region in the semiconductor substrate; and

recessing the first insulation region and the second insulation region, wherein top surfaces of remaining portions of the first insulation region and the second insulation region are flat surfaces or divot surfaces, and wherein a portion of the semiconductor substrate between and adjoining removed portions of the first insulation region and the second insulation region forms a fin.

2. The method of claim 1, wherein the step of recessing comprises a dry etch.

3. The method of claim 1, wherein the step of recessing comprises a SiCoNi process.

4. The method of claim 3, wherein the SiCoNi process comprises using HF and NH₃ as process gases.

5. The method of claim 4, wherein the first insulation region and the second insulation region comprise silicon oxide.

6. The method of claim 1 further comprising forming a fin field effect transistor (FinFET) comprising:

forming a gate dielectric on a top surface and sidewalls of the fin; and

forming a gate electrode on the gate dielectric, wherein the gate electrode comprises portions directly over the first insulation region and the second insulation region.

7. The method of claim 1, wherein the top surfaces of the remaining portions of the first insulation region and the second insulation region have divot profiles.

8. The method of claim 7, wherein a highest point and a lowest point of the top surface of the first insulation region have a difference greater than about 5 nm.

9. The method of claim 1, wherein the top surfaces of the remaining portions of the first insulation region and the second insulation region are substantially flat.

10. A method of forming an integrated circuit structure, the method comprising:

providing a silicon substrate;

forming a plurality of shallow-trench isolation (STI) regions in the silicon substrate;

removing top portions of the plurality of STI regions using a SiCoNi process to form a first silicon fin and a second silicon fin, wherein the first silicon fin and the second silicon fin are horizontally between, and above, remaining lower portions of the plurality of STI regions; and

forming a FinFET comprising;

forming a gate dielectric on top surfaces and sidewalls of the first silicon fin and the second silicon fin; and

forming a gate electrode on the gate dielectric, wherein the gate electrode extends from directly over the first silicon fin to directly over the second silicon fin.

11. The method of claim 10, wherein the top surfaces of the lower portions of the plurality of STI regions are divot surfaces.

12. The method of claim 10, wherein the top surfaces of the lower portions of the plurality of STI regions are flat surfaces.

13. The method of claim 10, wherein the SiCoNi process comprises using HF and NH3 as process gases.

14. The method of claim 13, wherein the plurality of STI regions comprises silicon oxide.

15. The method of claim 10, wherein a divot top surface of one of the plurality of STI regions joins the first silicon fin at a point, and wherein the joint point is a lowest point of the divot top surface.

16. The method of claim 10, wherein one of the plurality of STI regions (an intermediate STI region) is between the first silicon fin and the second silicon fin, wherein a highest point of a top surface of the intermediate STI region is close to a middle line between the first silicon fin and the second silicon fin.

17. The method of claim 16, wherein a lowest point of the top surface of the intermediate STI region is close to, and is not, a joint point of the top surface of the intermediate STI region and the first silicon fin.