Method of Forming a Topside Contact to a Backside Terminal of a Semiconductor Device

• US 20110097894A1
• Filed: 12/30/2010
• Published: 04/28/2011
• Est. Priority Date: 10/02/2007
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Bruce Marchant, Hamza Yilmaz, Ihsiu Ho, John T. Andrews
• Inventors: Ho, Ihsiu, Yilmaz, Hamza, Andrews, John T., Marchant, Bruce
• Granted Patent: US 8,536,042 B2
• Time in Patent Office: Days
• US Class Current: 438/618
• CPC Class Codes: H01L 24/12 Structure, shape, material or disposition of the bump connectors prior to the connecting process
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7809 having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/872 Schottky diodes
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01055 Cesium [Cs]
• CPC Class Codes: H01L 2924/12032 Schottky diode
• CPC Class Codes: H01L 2924/13055 Insulated gate bipolar transistor [IGBT]
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/3025 Electromagnetic shielding

Abstract

A process for forming a vertically conducting semiconductor device includes providing a semiconductor substrate having a topside surface and a backside surface. The semiconductor substrate serves as a terminal of the vertically conducting device for biasing the vertically conducting device during operation. The process also includes forming an epitaxial layer extending over the topside surface of the semiconductor substrate but terminating prior to reaching an edge of the semiconductor substrate so as to form a recessed region along a periphery of the semiconductor substrate. The method also includes forming an interconnect layer extending into the recessed region but terminating prior to reaching an edge of the semiconductor substrate. The interconnect layer electrically contacts the topside surface of the semiconductor substrate in the recessed region to thereby provide a topside contact to the semiconductor substrate.

Claims

1-26. -26. (canceled)

27. A method of forming a vertically conducting semiconductor device, the method comprising:

providing a semiconductor substrate having a topside surface and a backside surface, the semiconductor substrate serving as a terminal of the vertically conducting device for biasing the vertically conducting device during operation;

forming an epitaxial layer extending over the topside surface of the semiconductor substrate but terminating prior to reaching an edge of the semiconductor substrate so as to form a recessed region along a periphery of the semiconductor substrate; and

forming an interconnect layer extending into the recessed region but terminating prior to reaching an edge of the semiconductor substrate, the interconnect layer electrically contacting the topside surface of the semiconductor substrate in the recessed region to thereby provide a topside contact to the semiconductor substrate.

28. The method of claim 27 wherein the recessed region extends along an entire perimeter of the semiconductor substrate.

29. The method of claim 27 wherein the interconnect layer extends partially into the recessed region.

30. The method of claim 29 wherein the step of forming an epitaxial layer comprises:

selectively exposing a portion of the epitaxial layer using a photolithography process; and

removing a portion of the epitaxial layer using an etch process.

31. The method of claim 30 wherein the etch process comprises a wet etch process.

32. The method of claim 30 wherein the etch process comprises a dry silicon etch process.

33. The method of claim 27 further comprising:

prior to forming the interconnect layer, implanting dopants to form an implant region in the portion of the semiconductor substrate extending in the recessed region, the dopants being of the same conductivity type as the semiconductor substrate.

34. The method of claim 33 wherein the dopants are further implanted into a sloped sidewall of the epitaxial layer.

35. The method of claim 27 wherein the epitaxial layer is formed using a selective epitaxial growth process.

36. The method of claim 27 further comprising:

forming a passivation layer, the passivation layer having contact holes for exposing the surface areas of the interconnect layer for purposes of receiving an external connection.

37. The method of claim 27 further comprising:

forming an additional interconnect layer contacting the backside surface of the semiconductor substrate.