SYSTEM AND METHOD FOR HARDWARE ACCELERATION OF A SOFTWARE TRANSACTIONAL MEMORY
First Claim
1. A method for responding to an eviction or non-local writing (i.e., writing by another thread) of certain line(s) in a local cache of a cache-coherent shared-memory computer, the method comprising:
- (a) registering an alert handler for each thread that is interested in the eviction or non-local writing of said certain line(s) in the local cache;
(b) receiving indications from certain thread(s) of the line(s) for which the eviction or non-local writing is of interest, and marking said line(s) in the local cache; and
(c) upon the eviction or non-local writing of a marked line, effecting in each interested thread an immediate subroutine call to the alert handler of the thread, without changing a state of the local cache.
2 Assignments
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Accused Products
Abstract
In a transactional memory technique, hardware serves simply to optimize the performance of transactions that are controlled fundamentally by software. The hardware support reduces the overhead of common TM tasks—conflict detection, validation, and data isolation—for common-case bounded transactions. Software control preserves policy flexibility and supports transactions unbounded in space and in time. The hardware includes 1) an alert-on-update mechanism for fast software-controlled conflict detection; and 2) programmable data isolation, allowing potentially conflicting readers and writers to proceed concurrently under software control.
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Citations
42 Claims
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1. A method for responding to an eviction or non-local writing (i.e., writing by another thread) of certain line(s) in a local cache of a cache-coherent shared-memory computer, the method comprising:
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(a) registering an alert handler for each thread that is interested in the eviction or non-local writing of said certain line(s) in the local cache; (b) receiving indications from certain thread(s) of the line(s) for which the eviction or non-local writing is of interest, and marking said line(s) in the local cache; and (c) upon the eviction or non-local writing of a marked line, effecting in each interested thread an immediate subroutine call to the alert handler of the thread, without changing a state of the local cache. - View Dependent Claims (2, 3, 4, 5)
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6. A method for choosing whether to commit speculative writes in a cache-coherent shared-memory computer in which such writes have been indicated, and their lines so marked in a local cache, the method comprising:
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(a) distinguishing, in a cache coherence protocol, between ordinary and speculative requests for exclusive access to a line; (b) retaining, in the local cache, lines that have been speculatively written, despite speculative remote requests for exclusive access to those lines; and (c) providing an atomic conditional-validate operation which attempts to update a location that has not been speculatively written, which, if successful, makes all speculatively written lines in the local cache appear to have been non-speculatively written, and which, if unsuccessful, makes all speculatively written or threatened lines in the local cache appear to be invalid. - View Dependent Claims (7, 8, 9, 10, 11, 12, 13, 14)
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15. A system for managing a computer memory which is accessible to a plurality of threads responding to an eviction or non-local writing (i.e., writing by another thread) of certain line(s) in a local cache of a cache-coherent shared-memory computer, the system comprising:
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a plurality of caches in communication with the computer memory; and a processor or processors for; (a) registering an alert handler for each thread that is interested in the eviction or non-local writing of said certain line(s) in the local cache; (b) receiving indications from each of certain thread(s) of the line(s) for which the eviction or non-local writing is of interest, and marking said line(s) in the local cache; and (c) upon the eviction or non-local writing of a marked line, effecting in each interested thread an immediate subroutine call to the alert handler of the thread, without changing a state of the local cache. - View Dependent Claims (16, 17, 18, 19)
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20. A system for choosing whether to commit speculative writes in a cache-coherent shared-memory computer in which such writes have been indicated, and their lines so marked in a local cache, the system comprising:
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a plurality of caches in communication with the computer memory; and a processor or processors for; (a) distinguishing, in a cache coherence protocol, between ordinary and speculative requests for exclusive access to a line; (b) retaining, in the local cache, lines that have been speculatively written, despite speculative remote requests for exclusive access to those lines; and (c) providing an atomic conditional-validate operation which attempts to update a location that has not been speculatively written, which, if successful, makes all speculatively written lines in the local cache appear to have been non-speculatively written, and which, if unsuccessful, makes all speculatively written or threatened lines in the local cache appear to be invalid. - View Dependent Claims (21, 22, 23, 24, 25, 26, 27, 28)
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29. An article of manufacture for responding to an eviction or non-local writing (i.e., writing by another thread) of certain line(s) in a local cache of a cache-coherent shared-memory computer, the article of manufacture comprising:
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a computer-readable storage medium; and code, stored on the computer-readable storage medium, for controlling a processor or processors for; (a) registering an alert handler for each thread that is interested in the eviction or non-local writing of said certain line(s) in the local cache; (b) receiving indications from each of certain thread(s) of the line(s) for which the eviction or non-local writing is of interest, and marking said line(s) in the local cache; and (c) upon the eviction or non-local writing of a marked line, effecting in each interested thread an immediate subroutine call to the alert handler of the thread, without changing a state of the local cache. - View Dependent Claims (30, 31, 32, 33)
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34. An article of manufacture for choosing whether to commit speculative writes in a cache-coherent shared-memory computer in which such writes have been indicated, and their lines so marked in a local cache, the article of manufacture comprising:
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a computer-readable storage medium; and code, stored on the computer-readable storage medium, for controlling a processor or processors for; (a) distinguishing, in a cache coherence protocol, between ordinary and speculative requests for exclusive access to a line; (b) retaining, in the local cache, lines that have been speculatively written, despite speculative remote requests for exclusive access to those lines; and (c) providing an atomic conditional-validate operation which attempts to update a location that has not been speculatively written, which, if successful, makes all speculatively written lines in the local cache appear to have been non-speculatively written, and which, if unsuccessful, makes all speculatively written or threatened lines in the local cache appear to be invalid. - View Dependent Claims (35, 36, 37, 38, 39, 40, 41, 42)
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Specification