MULTI-THREADING PROCESSORS, INTEGRATED CIRCUIT DEVICES, SYSTEMS, AND PROCESSES OF OPERATION AND MANUFACTURE

• US 20110099355A1
• Filed: 01/06/2011
• Published: 04/28/2011
• Est. Priority Date: 08/30/2004
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Tran, Thang
• Granted Patent: US 9,389,869 B2
• Time in Patent Office: Days
• US Class Current: 712/217
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: G06F 9/30181 Instruction operation extension or modification
• CPC Class Codes: G06F 9/30189 according to execution mode, e.g. mode flag
• CPC Class Codes: G06F 9/324 using program counter relative addressing
• CPC Class Codes: G06F 9/3822 Parallel decoding, e.g. parallel decode units
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/3838 Dependency mechanisms, e.g. register scoreboarding
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3854 Instruction completion, e.g. retiring, committing or graduating
• CPC Class Codes: G06F 9/3858 Result writeback, i.e. updating the architectural state or memory
• CPC Class Codes: G06F 9/3861 Recovery, e.g. branch miss-prediction, exception handling error detection or correction G06F11/00
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: G06F 9/3888 controlled by a single instruction for multiple threads [SIMT] in parallel

Abstract

A multi-threaded microprocessor (1105) for processing instructions in threads. The microprocessor (1105) includes first and second decode pipelines (1730.0, 1730.1), first and second execute pipelines (1740, 1750), and coupling circuitry (1916) operable in a first mode to couple first and second threads from the first and second decode pipelines (1730.0, 1730.1) to the first and second execute pipelines (1740, 1750) respectively, and the coupling circuitry (1916) operable in a second mode to couple the first thread to both the first and second execute pipelines (1740, 1750). Various processes of manufacture, articles of manufacture, processes and methods of operation, circuits, devices, and systems are disclosed.

Claims

1. A multi-threaded microprocessor for processing instructions in threads, the microprocessor comprising:

first and second instruction dependency scoreboards;

first and second instruction input coupling circuits each having a coupling input and first and second coupling outputs and together operable to selectively feed said first and second instruction dependency scoreboards; and

output coupling logic having first and second coupling inputs fed by said first and second scoreboards, and having first and second instruction issue outputs.

2. The multi-threaded microprocessor claimed in claim 1 further comprising first and second instruction queues respectively coupled to the coupling inputs of said first and second instruction input coupling circuits.

3. The multi-threaded microprocessor claimed in claim 1 further comprising a control logic circuit operable to supply a first selector signal to said first instruction input coupling circuit and to said output logic, said first selector signal representing dual issue by said first scoreboard.

4. The multi-threaded microprocessor claimed in claim 3 wherein said control logic circuit is operable to supply a second selector signal to said second instruction input coupling circuit and to said output logic, said second selector signal representing dual issue by said second scoreboard.

5. The multi-threaded microprocessor claimed in claim 1 further comprising first and second execute pipelines respectively coupled to said instruction issue outputs of said output logic.

6. The multi-threaded microprocessor claimed in claim 1 further comprising first and second decode pipelines respectively coupled to a corresponding coupling input of said first and second instruction input coupling circuits.

7. The multi-threaded microprocessor claimed in claim 1 further comprising scoreboard routing circuitry and wherein said scoreboards share said scoreboard routing circuitry together.