MULTI-THREADING PROCESSORS, INTEGRATED CIRCUIT DEVICES, SYSTEMS, AND PROCESSES OF OPERATION AND MANUFACTURE

• US 20110099393A1
• Filed: 01/06/2011
• Published: 04/28/2011
• Est. Priority Date: 08/30/2004
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Tran, Thang
• Granted Patent: US 9,015,504 B2
• Time in Patent Office: Days
• US Class Current: 713/300
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: G06F 9/30181 Instruction operation extension or modification
• CPC Class Codes: G06F 9/30189 according to execution mode, e.g. mode flag
• CPC Class Codes: G06F 9/324 using program counter relative addressing
• CPC Class Codes: G06F 9/3822 Parallel decoding, e.g. parallel decode units
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/3838 Dependency mechanisms, e.g. register scoreboarding
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3854 Instruction completion, e.g. retiring, committing or graduating
• CPC Class Codes: G06F 9/3858 Result writeback, i.e. updating the architectural state or memory
• CPC Class Codes: G06F 9/3861 Recovery, e.g. branch miss-prediction, exception handling error detection or correction G06F11/00
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: G06F 9/3888 controlled by a single instruction for multiple threads [SIMT] in parallel

Abstract

A multi-threaded microprocessor (1105) for processing instructions in threads. The microprocessor (1105) includes first and second decode pipelines (1730.0, 1730.1), first and second execute pipelines (1740, 1750), and coupling circuitry (1916) operable in a first mode to couple first and second threads from the first and second decode pipelines (1730.0, 1730.1) to the first and second execute pipelines (1740, 1750) respectively, and the coupling circuitry (1916) operable in a second mode to couple the first thread to both the first and second execute pipelines (1740, 1750). Various processes of manufacture, articles of manufacture, processes and methods of operation, circuits, devices, and systems are disclosed.

Claims

1. A multi-threaded microprocessor for processing instructions in threads, the microprocessor comprising:

at least one processor pipeline for the instructions;

a storage for a thread power management configuration; and

a power control circuit coupled to said at least one processor pipeline and responsive to said storage for thread power management configuration to control power used by different parts of the at least one processor pipeline depending on the threads.

2. The multi-threaded microprocessor claimed in claim 1 wherein said power control circuit is operable to activate or deactivate different parts of the at least one processor pipeline depending on the threads.

3. The multi-threaded microprocessor claimed in claim 1 wherein said power control circuit is operable to establish different power voltages in different parts of the at least one processor pipeline depending on the threads.

4. The multi-threaded microprocessor claimed in claim 1 wherein said power control circuit is operable to establish different clock rates in different parts of the at least one processor pipeline depending on the threads.

5. The multi-threaded microprocessor claimed in claim 1 wherein said processor pipeline includes a plurality of decode pipelines and a plurality of execute pipelines.

6. The multi-threaded microprocessor claimed in claim 5 wherein said power control circuit is operable to provide a thread-specific power control to different ones of said decode pipelines.

7. The multi-threaded microprocessor claimed in claim 5 wherein said power control circuit is operable to provide a thread-specific power control to a respective number of said execute pipelines depending on how many execute pipelines are assigned to a given thread.

8. A telecommunications unit comprising:

a limited-energy source;

a wireless modem coupled to said limited energy source;

a multi-threaded microprocessor coupled to said limited energy source and to said wireless modem and said microprocessor operable for processing instructions in threads and including at least one processor pipeline for the instructions, a storage for a thread power management configuration, and a power control circuit coupled to said at least one processor pipeline and responsive to said storage for thread power management configuration to control power used by different parts of the at least one processor pipeline depending on the threads; and

a microphone coupled to said multi-threaded microprocessor.