ENHANCED CONTROL IN SCAN TESTS OF INTEGRATED CIRCUITS WITH PARTITIONED SCAN CHAINS

• US 20110099442A1
• Filed: 10/23/2009
• Published: 04/28/2011
• Est. Priority Date: 10/23/2009
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Hales, Alan David, Tiwari, Rajesh Kumar, Parekhji, Rubin Ajit, Ravi, Srivaths, Nakidi, Srujan Kumar
• Granted Patent: US 8,205,125 B2
• Time in Patent Office: Days
• US Class Current: 714/729
• CPC Class Codes: G01R 31/318533 using scanning techniques, e.g. LSSD, Boundary Scan, JTAG

Abstract

A test controller implemented in an integrated circuit (IC) with partitioned scan chains provides enhanced control in performing scan tests. According to an aspect, a test controller can selectively control scan-in, scan-out and capture phases of scan tests for different scan chains of the IC to be independent. The number of pins required to interface the test controller with an external tester is less than the number of partitions that the test controller can support. According to another aspect, an IC includes a register corresponding to each partition to support transition fault (or LOS) testing. According to another aspect, an IC with partitioned scan chains includes serial to parallel and parallel to serial converters, thereby minimizing the external pins required to support scan tests.

Claims

1. An integrated circuit (IC) comprising:

a plurality of memory elements operable as a plurality of scan chains; and

a test controller designed to receive a digital data indicating a corresponding specific duration in which each of said plurality of scan chains is to be placed in a scan mode,

said test controller to scan data in each of said plurality of scan chains in the corresponding duration indicated by said digital data,

said digital data having the ability to indicate each of said specific durations independently,

said digital data being received from a set of pins connected to an external tester,

wherein the number of said set of pins is lesser than the number of said plurality of scan chains.

2. The IC of claim 1, wherein each of said plurality of scan chains is contained in a corresponding one of a plurality of partitions,

wherein the number of said plurality of partitions is greater than 2, such that said test controller scans the scan data of the scan chains in corresponding partitions in respective durations which are independent of each other.

3. The IC of claim 2, wherein said number of said set of pins equals 1.

4. The IC of claim 1, wherein said test controller comprises:

a delay register and a count register for each of said plurality of scan chains, the delay registers and the count registers being coupled as a chain to receive corresponding values via said set of pins,

wherein a value loaded in said count register indicates the length of the corresponding duration of scan of the corresponding scan chain, and the delay register indicates a delay after a start signal at which the scan duration begins.

5. The IC of claim 4, wherein said test controller further comprises:

a plurality of stages, each stage to receive the values stored in the corresponding delay register and the count register, and to generate a corresponding one of a plurality of a partition select signal,

said partition select signal indicating the specific duration for which scan of the corresponding scan chain is performed.

6. The IC of claim 5, wherein each of said plurality of stages comprises:

a delay element to delay said start signal and provide a delay signal as an output;

a counter to start counting upon receiving a transition of said delay signal;

a comparator to compare the values in said counter and said count register corresponding to the same stage; and

a set of combinational gates to generate said partition select signal based on the outputs of said comparator and said delay signal.

7. The IC of claim 6, wherein said test controller further comprises a bypass register for each of said plurality of stages except an initial stage, wherein said start signal is a local start signal for each of said plurality of stages except said initial stage, said start signal being a global start signal received from said external tester for said initial stage, wherein each of said plurality of stages except said initial stage comprises:

a multiplexer to select either said global start signal or an end signal from a prior stage as said local start signal depending on a select value received from the corresponding bypass register, wherein said end signal indicates the end of the scan duration for the prior stage.

8. The IC of claim 5, wherein said test controller further comprises:

a first logic gate corresponding to each of said plurality of stages, wherein the first logic gate gates a global master clock received from said external tester with the corresponding partition select signal to generate a partition clock signal which clocks each of the memory elements in corresponding scan chain; and

a second logic gate corresponding to each of said plurality of stages, wherein the second logic gate gates a master scan enable received from said external tester with the corresponding partition select signal to generate a partition scan enable signal for the corresponding scan chain.

9. The IC of claim 8, wherein a corresponding one of a plurality of test vectors is scanned into a respective one of said plurality of scan chains according to the corresponding partition scan enable and the partition clock signal,

wherein said plurality of test vectors are designed to perform a stuck at fault test in said IC.

10. The IC of claim 9, wherein said plurality of scan chains includes a first scan chain and a second scan chain,

said first scan chain to scan-in each of a first sequence of bits, except a last bit, of a first vector in a first sequence of clock cycles,

said second scan chain to scan-in each of a second sequence of bits of a second vector in a second sequence of clock cycles, at least some of said second sequence of clock cycles following a last one of said first sequence of clock cycles;

a register to store said last bit prior to a last clock cycle of said second sequence of clock cycles,

wherein the bit stored in said register is scanned in along with said last clock cycle of said second sequence of clock cycles and at least one of said first scan chain and said second scan chain is placed in a capture phase following said last clock cycle to perform a transition fault test.

11. The IC of claim 10, further comprising a multiplexor to receive each of said first sequence of bits on a first path and the value in said register on a second path and select one of the two inputs based on a select value,

wherein said test controller provides said select value with one value during each of said first sequence of clock cycles, and another value during said last clock cycle of said second sequence of clock cycles.

12. The IC of claim 11 further comprising:

a serial to parallel converter (SPC) to receive a sequence of data units at a first frequency on a first path, said SPC to form a sequence of larger data units by concatenating a plurality of data units contained in said sequence of data units, said SPC to provide said sequence of larger data units at a lower frequency than said first frequency on a second path containing a second set of lines, each of said second set of lines carrying one bit of said sequence of larger data units in each scan clock cycle at said lower frequency; and

wherein each scan chain in said plurality of scan chains receives successive ones of a corresponding sequence of bits on a corresponding one of said second set of lines,

wherein said first path contains a first set of lines to connect to corresponding pins of said external tester, wherein a number of lines in said first path is lesser than a number of lines in said second path,

whereby said IC operates with a fewer pins interfacing with said external tester compared to the number of scan chains in said plurality of scan chains.

13. The IC of claim 12, further comprising:

a parallel to serial converter (PSC) to receive evaluation outputs from said plurality of scan chains on a third path at a scan out frequency, said third path containing a third set of lines, each line for transferring a bit of the scan output of a corresponding scan chain in one scan out cycle, the bits received in each scan out cycle from all of said plurality of scan chains forming an output unit such that a sequence of output units are received in successive scan out cycles, said PSC to covert each output unit as a plurality of smaller units by splitting each output unit into multiple smaller units,

wherein said smaller units are transmitted at a higher frequency than said scan out frequency,

wherein each bit of a smaller unit is transferred on a corresponding one of a fourth set of pins to said external tester such that the number of pins required to interface with said external tester are also reduced.

14. An integrated circuit (IC) comprising:

a first plurality of memory elements operable as a first scan chain and a second plurality of memory elements operable as a second scan chain,

said first scan chain to scan-in each of a first sequence of bits, except a last bit, of a first vector in a first sequence of clock cycles,

said second scan chain to scan-in each of a second sequence of bits of a second vector in a second sequence of clock cycles, at least some of said second sequence of clock cycles following a last one of said first sequence of clock cycles;

a register to store said last bit prior to a last clock cycle of said second sequence of clock cycles,

wherein the bit stored in said register is scanned in along with said last clock cycle of said second sequence of clock cycles and at least one of said first scan chain and said second scan chain is placed in a capture phase following said last clock cycle to perform a transition fault test.

15. The IC of claim 14, wherein said first scan chain and said second scan chain have the ability to be scanned in independent durations.

16. The IC of claim 14, further comprising:

a multiplexer to receive each of said first sequence of bits on a first path and the value in said register on a second path and select one of the two inputs based on a select value; and

a test controller to generate said select value with one value during each of said first sequence of clock cycles, and another value during said last clock cycle of said second sequence of clock cycles.

17. An integrated circuit (IC) comprising:

a serial to parallel converter (SPC) to receive a sequence of data units at a first frequency on a first path, said SPC to form a sequence of larger data units by concatenating a plurality of data units contained in said sequence of data units, said SPC to provide said sequence of larger data units at a lower frequency than said first frequency on a second path containing a second set of lines, each of said second set of lines carrying one bit of said sequence of larger data units in each scan clock cycle at said lower frequency; and

a plurality of memory elements operable as a plurality of scan chains, each scan chain designed to receive successive ones of a corresponding sequence of bits as a scan chain on a corresponding one of said second set of lines,

wherein said first path contains a first set of lines to connect to corresponding pins of a tester, wherein a number of lines in said first path is lesser than a number of lines in said second path,

whereby said IC operates with a fewer pins interfacing with said tester compared to the number of scan chains.

18. The IC of claim 17, wherein said first frequency is an integer times said lower frequency, said SPC comprising:

twice said integer number of units organized in the form of two rows and integer number of columns, each unit containing a register and an input multiplexer, the input multiplexer being designed to store said sequence of data units in row-wise and then column-wise fashion; and

a number of output multiplexors, each associated with one column and to select the output of one of the number of registers in the associated column in each of said lower frequency clock cycles,

the output of all of said number of output multiplexors being concatenated in each lower frequency clock cycle to form one of said larger data units.

19. The IC of claim 17, further comprising:

a parallel to serial converter (PSC) to receive evaluation outputs from said plurality of scan chains on a third path at a scan out frequency, said third path containing a third set of lines, each line for transferring a bit of the scan output of a corresponding scan chain in one scan out cycle, the bits received in each scan out cycle from all of said plurality of scan chains forming an output unit such that a sequence of output units are received in successive scan out cycles, said PSC to convert each output unit as a plurality of smaller units by splitting each output unit into multiple smaller units,

wherein said smaller units are transmitted at a higher frequency than said scan out frequency,

wherein each bit of a smaller unit is transferred on a corresponding one of a fourth set of pins to said tester such that the number of pins required to interface with said tester are also reduced.

20. The IC of claim 19, wherein said first frequency is an integer times said lower frequency, wherein said PSC comprises:

a multiplexer to receive said evaluation outputs at said scan out frequency and to select successive ones of 1/integer portion of the received evaluation output in each of said higher frequency clock cycle as said smaller unit.