ERROR DETECTION/CORRECTION BASED MEMORY MANAGEMENT

• US 20110099458A1
• Filed: 10/27/2009
• Published: 04/28/2011
• Est. Priority Date: 10/27/2009
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Martin, Tim, Reche, Cory, Nevill, Lee
• Granted Patent: US 8,312,349 B2
• Time in Patent Office: Days
• US Class Current: 714/763
• CPC Class Codes: G06F 11/073 in a memory management context, e.g. virtual memory or cache management memory management G06F12/00; testing of static memory units G11C29/00
• CPC Class Codes: G06F 11/076 by exceeding a count or rate limit, e.g. word- or bit count limit
• CPC Class Codes: G06F 11/0793 Remedial or corrective actions recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 11/2053 where persistent mass storage functionality or persistent mass storage control functionality is redundant error detection or correction in information storage based on relative movement between record carrier and transducer G11B20/18
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: H03M 13/15 Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes H03M13/17 takes precedence
• CPC Class Codes: H03M 13/1515 Reed-Solomon codes
• CPC Class Codes: H03M 13/152 Bose-Chaudhuri-Hocquenghem [BCH] codes
• CPC Class Codes: H03M 13/19 Single error correction without using particular properties of the cyclic codes, e.g. Hamming codes, extended or generalised Hamming codes

Abstract

The present disclosure includes methods, devices, and systems for error detection/correction based memory management. One embodiment includes performing a read operation with respect to a particular group of memory cells of a memory device and, if the read operation results in an uncorrectable error, determining whether to retire the particular group of memory cells in response to a status of an indicator corresponding to the particular group of memory cells, wherein the status of the indicator indicates whether the particular group of memory cells has a previous uncorrectable error associated therewith.

Claims

1. A method for error detection/correction based memory management, comprising:

performing a read operation with respect to a particular group of memory cells of a memory device; and

if the read operation results in an uncorrectable error, determining whether to retire the particular group of memory cells in response to a status of an indicator corresponding to the particular group of memory cells, wherein the status of the indicator indicates whether the particular group of memory cells has a previous uncorrectable error associated therewith.

2. The method of claim 1, wherein the method includes updating the status of the indicator corresponding to the particular group of memory cells when the read operation results in an uncorrectable error.

3. The method of claim 2, wherein updating the status of the indicator comprises setting a flag.

4. The method of claim 2, wherein updating the status of the indicator comprises incrementing a counter.

5. The method of claim 1, wherein the method includes storing the indicator within the memory device.

6. The method of claim 1, wherein performing a read operation with respect to a particular group of memory cells of a memory device comprises performing a read operation with respect to a particular block of memory cells.

7. The method of claim 1, wherein performing a read operation with respect to a particular group of memory cells of a memory device comprises performing a read operation with respect to a particular page of data.

8. The method of claim 1, wherein the method includes retiring the particular group of memory cells if the status of the indicator indicates that a threshold number of uncorrectable errors associated with the particular group of memory cells has been reached.

9. The method of claim 8, wherein the threshold number of uncorrectable errors associated with the particular group of memory cells is different from a threshold number of uncorrectable errors associated with another group of memory cells of the memory device.

10. The method of claim 1, wherein the method includes storing associated error detection/correction information along with the data being read.

11. The method of claim 1, wherein the method includes retiring the particular group of memory cells if the status of the indicator indicates the particular group of memory cells has a previous uncorrectable error associated therewith.

12. A method for error detection/correction based memory management, comprising:

determining an uncorrectable error has occurred in association with a read operation performed with respect to a particular group of memory cells of a memory device;

determining a status of an indicator corresponding to the particular group of memory cells, wherein the status of the indicator indicates whether the particular group of memory cells has a previous uncorrectable error associated therewith; and

determining whether to retire the particular group of memory cells in response to the determined status of the indicator.

13. The method of claim 12, wherein the method includes updating the status of the indicator corresponding to the particular group of memory cells in response to a determination that an uncorrectable error has occurred in association with the read.

14. The method of claim 12, wherein the method includes retiring the particular group of memory cells when the status of the indicator corresponding to the particular group of memory cells indicates that a threshold number of uncorrectable errors have occurred in association with read operations performed with respect to the particular group of memory cells.

15. The method of claim 14, wherein the threshold number is at least two.

16. The method of claim 14, wherein the threshold number is variable.

17. The method of claim 16, wherein the threshold number is decreased based, at least partially, on at least one of:

an age of the memory device; and

a number of program/erase cycles performed with respect to the particular group of memory cells.

18. The method of claim 12, wherein an uncorrectable error is an error not correctable by an error detection/correction controller associated with the memory device.

19. The method of claim 12, wherein the method includes tracking a ratio of total uncorrectable errors to total data throughput associated with the memory device.

20. The method of claim 19, wherein the method includes providing the ratio to a host coupled to the memory device.

21. A memory system, comprising:

a memory device; and

a controller coupled to the memory device and configured to, for each of a number of particular groups of memory cells of the memory device;

update a status of an indicator corresponding to the particular group of memory cells in response to a read operation performed with respect to the particular group of memory cells resulting in an uncorrectable error; and

determine, in response to the status of the indicator, whether to retire the particular group of memory cells in response to a subsequent read operation performed with respect to the particular group of memory cells resulting in an uncorrectable error.

22. The memory system of claim 21, wherein each of the number of groups of memory cells of the memory device is a block of non-volatile memory cells that are erased together as a group.

23. The memory system of claim 22, wherein the indicator corresponding to the particular block is stored within the particular block.

24. The memory system of claim 21, wherein the indicator corresponding to the particular block is stored, at least temporarily, in a volatile memory portion of the memory device.

25. The memory system of claim 21, wherein the indicator corresponding a particular group of memory cells is a flag, and wherein the controller is configured to retire a particular the particular group of memory cells when a status of the flag indicates the particular group of memory cells has a previous uncorrectable error associated therewith.

26. The memory system of claim 21, wherein the system includes error correction code (ECC) circuitry configured to:

detect errors in data being read during read operations performed on the memory device by using ECC information associated with the data being read; and

correct up to a threshold number of detected errors; and

wherein an uncorrectable error is an error not correctable by the ECC circuitry.

27. The memory system of claim 21, wherein the indicator is a counter, and wherein the controller is configured to retire the particular group of memory cells if the status of the counter indicates a threshold number of uncorrectable errors associated with the particular group of memory cells has been reached.

28. The memory system of claim 21, wherein each of the number of groups of memory cells of the memory device includes a number of memory cells associated with a corresponding page of data.

29. A memory system, comprising:

a memory device having groups of memory cells; and

a controller coupled to the memory device and configured to;

determine whether an uncorrectable error has occurred in association with a read operation performed with respect to a particular group of memory cells;

determine a status of an indicator corresponding to the particular block, wherein the status of the indicator indicates whether the particular group of memory cells has a previous uncorrectable error associated therewith; and

determine whether to retire the particular group of memory cells in response to the determined status of the indicator.

30. The memory system of claim 29, wherein the controller is configured to retire the particular group of memory cells when the determined status of the indicator indicates that the particular group of memory cells has a previous uncorrectable error associated therewith.

31. The memory system of claim 29, wherein the controller is configured to update the status of the indicator corresponding to the particular group of memory cells in response to a determination that an uncorrectable error has occurred in association with a read operation performed with respect to the particular group of memory cells.

32. The memory system of claim 29, wherein the indicator is a counter, and wherein the controller is configured to retire the particular group of memory cells when the status of the counter indicates that a threshold number of uncorrectable errors have occurred in association with read operations performed with respect to the particular group of memory cells.

33. The memory system of claim 29, wherein the controller includes a tracking component configured to track a ratio of total uncorrectable errors to total data throughput associated with the memory device.

34. The memory system of claim 29, wherein the controller is configured to provide the ratio to a host coupled to the memory device.