Pattern Selection for Full-Chip Source and Mask Optimization

• US 20110099526A1
• Filed: 10/28/2010
• Published: 04/28/2011
• Est. Priority Date: 10/28/2009
• Status: Active Grant

• Current Assignee: ASML Netherlands BV (ASML Holding NV)
• Original Assignee: ASML Netherlands BV (ASML Holding NV)
• Inventors: Liu, Hua-Yu
• Granted Patent: US 8,438,508 B2
• Time in Patent Office: Days
• US Class Current: 716/54
• CPC Class Codes: G03F 1/36 Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
• CPC Class Codes: G03F 7/70125 Use of illumination settings tailored to particular mask patterns details of setting means G03F7/70091
• CPC Class Codes: G03F 7/70425 Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
• CPC Class Codes: G03F 7/70441 Optical proximity correction [OPC]
• CPC Class Codes: G03F 7/705 Modelling or simulating from physical phenomena up to complete wafer processes or whole workflow in wafer productions
• CPC Class Codes: G03F 7/70666 Aerial image, i.e. measuring the image of the patterned exposure light at the image plane of the projection system
• CPC Class Codes: G06F 30/00 Computer-aided design [CAD]
• CPC Class Codes: G06F 30/20 Design optimisation, verification or simulation optimisation, verification or simulation of circuit designs G06F30/30
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

The present invention relates to lithographic apparatuses and processes, and more particularly to tools for optimizing illumination sources and masks for use in lithographic apparatuses and processes. According to certain aspects, the present invention enables full chip pattern coverage while lowering the computation cost by intelligently selecting a small set of critical design patterns from the full set of clips to be used in source and mask optimization. Optimization is performed only on these selected patterns to obtain an optimized source. The optimized source is then used to optimize the mask (e.g. using OPC and manufacturability verification) for the full chip, and the process window performance results are compared. If the results are comparable to conventional full-chip SMO, the process ends, otherwise various methods are provided for iteratively converging on the successful result.

Claims

1. A method for optimizing a lithographic process for imaging a portion of a design onto a substrate, the method comprising:

selecting a subset of patterns from the portion of the design;

optimizing an illumination source for the lithographic process for imaging the selected subset of patterns; and

using the optimized illumination source for optimizing the portion of the design for being imaged in the lithographic process.

2. A method according to claim 1, wherein the portion of the design comprises a full chip.

3. A method according to claim 1, wherein the portion of the design comprises clips and wherein the step of selecting a subset of patterns comprises:

identifying a full set of clips from the design;

selecting a subset of clips from the full set of clips;

wherein the step of optimizing comprises optimizing an illumination source for the lithographic process for imaging the selected subset of clips; and

wherein the step of using comprises using the optimized illumination source for optimizing the full set of clips for being imaged in the lithographic process.

4. A method according to claim 1, wherein the selecting step includes:

calculating diffraction order distributions for patterns in the portion of the design;

grouping said patterns into a plurality of groups based on the calculated diffraction order distributions; and

selecting one or more representative patterns from each of the groups as the subset of patterns.

5. A method according to claim 1, wherein the selecting step includes:

identifying one or more memory patterns in the portion of the design;

pre-optimizing the illumination source for the one or more memory patterns;

using the pre-optimized illumination source to determine potential hot spots in the portion of the design; and

selecting the subset of patterns based on the determined potential hot spots.

6. A method according to claim 1, wherein the selecting step includes:

identifying an original illumination source for the lithographic process;

using the original illumination source to determine potential hot spots in the portion of the design; and

selecting the subset of patterns based on the determined potential hot spots.

7. A method according to claim 5, wherein the method further comprises a step of:

calculating a severity score for a hot spot; and

selecting the hot spot having a predefined severity score or selecting the hot spot having a severity score within a predefined severity score range.

8. A method according to claim 6, wherein the method further comprises a step of:

calculating a severity score for a hot spot; and

selecting the hot spot having a predefined severity score or selecting the hot spot having a severity score within a predefined severity score range.

9. A method according to claim 1, wherein the selecting step includes:

grouping patterns in the portion of the design by design type into a plurality of groups;

sorting the patterns in each group by pitch and feature type to determine an optimal pattern in each group; and

selecting the optimal pattern in each group as the subset of patterns.

10. A method according to claim 1, wherein the selecting step includes:

identifying a simulation model of the lithographic process;

using the model to estimate process parameter sensitivities for patterns in the portion of the design; and

selecting the subset of patterns based on the estimated process parameter sensitivities.

11. A method according to claim 1, further comprising:

determining whether a lithographic process performance metric for the optimized subset of patterns is acceptable; and

if the determined metric is not acceptable, adding clips having potential hot spots to the subset of patterns and repeating the optimization steps.

12. A method according to claim 1, wherein the step of optimizing the illumination source includes simulating a lithographic process performance using a model of the lithographic process, the illumination source, and the subset of patterns to determine whether the performance is acceptable.

13. A method according to claim 1, wherein the step of optimizing the portion of the design includes performing optical proximity correction on certain of the patterns based on the optimized illumination source.

14. A computer readable medium having instructions recorded thereon, which when read by a computer, causes the computer to perform a method for optimizing a lithographic process for imaging a portion of a design onto a wafer according to claim 1.

15. A lithographic apparatus comprising:

an illumination system configured to provide a beam of radiation;

a support structure configured to support a patterning means, the patterning means serving to impart the radiation beam with a pattern in its cross-section;

a substrate table configured to hold a substrate; and

a projection system for projecting the patterned radiation beam onto a target portion of the substrate;

wherein the lithographic apparatus further comprises a processor for configuring the illumination system to generate the optimized illumination source according to the method for optimizing a lithographic process of claim 1.

16. A patterning means for imparting a radiation beam from an illumination system of a lithographic apparatus being configured for projecting this imparted beam via a projection system onto a target portion of a substrate, wherein the patterning means comprises an optimized portion of a design, wherein the optimized potion of the design is determined according to the method of optimizing a lithographic process of claim 1.

17. A method for optimizing a lithographic process for imaging a portion of a design onto a wafer, the method comprising:

identifying a full set of clips from the design;

selecting a subset of clips from the full set of clips;

optimizing an illumination source for the lithographic process for imaging the selected subset of clips; and

using the optimized illumination source for optimizing the full set of clips for being imaged in the lithographic process.

18. A method according to claim 17, wherein the selecting step includes:

calculating diffraction order distributions for each of the full set of clips;

grouping the full set of clips into a plurality of groups based on the calculated diffraction order distributions; and

selecting one or more representative clips from each of the groups as the subset.

19. A method according to claim 18, wherein the selecting step includes:

identifying one or more memory patterns in the full set of clips;

pre-optimizing the illumination source for the one or more memory patterns;

using the pre-optimized illumination source to determine potential hot spots in the full set of clips; and

selecting the subset based on the determined potential hot spots.

20. A method according to claim 17, wherein the selecting step includes:

identifying an original illumination source for the lithographic process;

using the original illumination source to determine potential hot spots in the full set of clips; and

selecting the subset based on the determined potential hot spots.

21. A method according to claim 17, wherein the selecting step includes:

grouping patterns in the full set of clips by design type into a plurality of groups;

sorting the patterns in each group by pitch and feature type to determine an optimal pattern in each group; and

selecting the optimal pattern in each group as the subset.

22. A method according to claim 17, wherein the selecting step includes:

identifying a simulation model of the lithographic process;

using the model to estimate process parameter sensitivities for each of the full set of clips; and

selecting the subset based on the estimated process parameter sensitivities.